Looking for a clock generator to support below needed clocks:
1x LVDS - 125MHz for QSGMII (low phase noise < 1ps),
1x LVDS - 125Mhz for Marvell PHY.
1x LVDS - 156.25MHz for 10GBASE-T (Xilinx Serdes)
3x LVDS - 200Mhz (DDR Clock & system Clock for FPGA)
The 125Mhz and 156.25MHz jitter mask is attached below:
Hi Eli,
you can try CDCM6208, it could generate all your necessary clocks with a 25MHz crystal. See attached configuration.
Hi,
See below and advise:
This is the plot I got. I rather use the integer divider for lowest Jitter.
I need help with the Loop Filter. I used following values (be below) and got Phase noise figure Marginal for 125MHz at 10K offset.
Ignore the 200Mhz, I need the 200MHz for DDR prior to CDCM6208 configuration. (couldn't find this frequency at pre-configuration options).
Hi Eli,
Suggest use higher charge pump current and wider loop bandwidth. For example, use 2.5mA CP current and set the loop bandwidth to 400kHz. Phase margin equals 70deg is fine.
Below is a plot also with 25MHz crystal input, 125MHz output that we took a couple of years ago. At 10kHz offset, the phase noise is close to -135dBc/Hz.
