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LMH1983 PLL4 Centre frequency

Other Parts Discussed in Thread: LMH1983

The data sheet shows that the Register 0x39 allows adjustment of the PLL4 centre frequency. Is there any further data available which describes the relationship between the register value and the corresponding PLL4 centre frequency? i.e. register value 0x7F = ???? PLL4 centre frequency

  • Hi John,

    The apps team responsible for this device has been contacted and will reply shortly.

    Thanks!

    Gabe

  • Hi John,

    I have used PLL4 to generate different clocks. Please below note the write up that i have related to this topic. 

    The LMH1983 SDI Video Audio clock generator has flexible audio clock, PLL4, to provide a wide range of the clock frequency as desired. The PLL4 VCO range operates from 1.3G to 1.6934GHz. The LMH1983 PLL4 has flexibility to allow the device to generate different audio clock rates provided the VCO frequency is centered in this range.

    The VCO range is divided down by the following equation:

    3*IS125M*2^(PLL4_DIV)

    The related registers are:

    PLL4 VCO Range Register: 0x039

    PLL4 VCO Divider Register: 0x34

    Register 0x34[7:4]: This bits set PLL4_DIV variable

    IS125M: Selects either divide by 4 or divide b5

    Procedure for changing the PLL4 clock frequency:

    1). Let’s say the desired frequency is 29.5MHz.

    2). Divide the lower limit of the range(1.3G) by the desired frequency(i.e 29.5MHz). (1.3E9/29.5E6)= 44.1

    3). Divide the upper limit of the range(1.6934GHz) by the desired frequency: (1.6934/29.5E6)=54.7

    4). Given the above two results, it means 3*IS125M*2^(PLL4_DIV) must be a number between 45 and 54

    5). Since IS125M either divide by 4 or divide by 5, the number between 45 to 54 has to be divisible either by 12 or 15

    6). Further, given 2^(PLL4_DIV) is either 1,2,4,….., or 32768 AND divisor ratio has to be between 45 to 54, PLL4_DIV has to be 2

    7). Thus 3*IS125M*2^(PLL4_DIV)= 3*4*2^(2)=3*4*4=48

    8). Finally, we should set the VCO range frequency, Reg 0x39, to 1.416GHz to generate exactly 29.5MHz. Using a value of Reg 0x39 = 0x21 achieves this result

    In summary, PLL4 output can be used to generate a range of frequency where it is genlocked to the PLL1(27MHz), HVF Signal, or 10MHz reference clock.

    Regards,,nasser

  • Hi Nasser, thank you for your reply.

    I have followed the method that you have described to determine the PLL4 frequency, but I still do not understand how to calculate the Reg 0x39 value. Can you tell me how you arrived at the value of 0x21 in the example? I have not been able to find any documented relationship between the VCO centre frequency and the Reg 0x39 value.

    regards

    John

  • Hi John,

    I did not calculate the Reg 0x39 content. I used a spectrum analyzer on the output of the PLL4 and changed Reg 0x39 value until i got the desired frequency. You can do a similar procedure as well. 

    Regards,,nasser

  • Hi Nasser,

    thank you for your help.

    regards

    John