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Clock Design Tool for LMK04828B

Other Parts Discussed in Thread: CLOCKDESIGNTOOL

Hello,

My customer have some questions about Clock Design Tool for LMK04828B.

I attached their configuration and results.

8304.ClockDesignTool_for_LMK04828B.pdf

Their configuration as follows.

<Customer Configuration>

 CLKinX=122.88MHz

 VCXO=30.72MHz

 PDF1=480kHz

 PDF2=30.72MHz

 VCO=2457.6MHz

 CLKout0=122.88MHz, LVDS

 CLKout1=122.88MHz, LVDS

[Q1]

CLKout0 and CLKout1 are the same configurations.

But the results of phase noise and RMS jitter are different.

Why is that ?

Is this because the models of additive jitter are different every output ? or Is it a bug ?

[Q2]

Our environment as follows.

<Customer Environment>

 (A) Windows XP (Japanese version)

<My Environment>

 (B) Windows XP mode (English version) on Windows Virtual PC on Windows 7 (Japanese version)

 (C) Windows 7 (Japanese version)

Clock Design Tool is always down when we try to load a saved states in all environments.

I attached the save state.

5808.save_state.zip

Why is that ?

Best Regards,

Hiroshi Katsunaga

  • Hi Katsunaga-san,

    A few comments about the attached .pdf. In the latest version of Clock Design Tool, CLKout0 is set to LVPECL while CLKout1 is LVDS. The difference in noise and noise floor will result in your mismatch of RMS jitter. Please update to the latest CDT to match this.

    I will look into why configurations are not loading correclty into CDT.

    Gabe

  • Hi Gabe-san,

    Thank you for your fast response.

    And I'm sorry for my late response.

    I understood your comment.

    *****************************************************************************************

    The noise floor of CLKout0 seems to be applied as it in LVPECL

    because the results are same when I set it in LVDS and when I set it in LVPECL. 

    We used the latest CDT (ver 1.3.6).

    I will close this thread.

    *****************************************************************************************

    Please confirm why  we cannot load it, and please improve CDT.

    Best Regards,

    Hiroshi Katsunaga