Hello,
My customer have some questions about Clock Design Tool for LMK04828B.
I attached their configuration and results.
8304.ClockDesignTool_for_LMK04828B.pdf
Their configuration as follows.
<Customer Configuration>
CLKinX=122.88MHz
VCXO=30.72MHz
PDF1=480kHz
PDF2=30.72MHz
VCO=2457.6MHz
CLKout0=122.88MHz, LVDS
CLKout1=122.88MHz, LVDS
[Q1]
CLKout0 and CLKout1 are the same configurations.
But the results of phase noise and RMS jitter are different.
Why is that ?
Is this because the models of additive jitter are different every output ? or Is it a bug ?
[Q2]
Our environment as follows.
<Customer Environment>
(A) Windows XP (Japanese version)
<My Environment>
(B) Windows XP mode (English version) on Windows Virtual PC on Windows 7 (Japanese version)
(C) Windows 7 (Japanese version)
Clock Design Tool is always down when we try to load a saved states in all environments.
I attached the save state.
Why is that ?
Best Regards,
Hiroshi Katsunaga