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Clock distribution chip for ADC12D1800

Other Parts Discussed in Thread: LMX2541, LMK01801, ADC12D1800, LMX2581, LMK04906

Hi,

We are planning to use ADC12D1800 in my application. In my board there will be two devices(12bit ADC from TI & front end Track & hold HMC661LC4B amplifer from Hittite) which  requires same clock of 3.1GHz. I planned to use LMX2541 PLL for clocking the ADC as well as track hold amplifer but LMX2541 has single channel o/p for this I planned to use LMK01801 has a clock distributor between PLL & ADC whether this will work ?

What will be the performance degradation due to LMK01801 in the chain?

Is there any other device which is better than LMK01801 ?

Whether LMX2541 shall drive LMK01801 directly ?

Note: My board has two independent analog channels, Two  adc channels two PLL chips both the channels are operating at different sampling frequency's. So I planed to use both the channels in the LMK01801 chip .

Regards,

Rajesh

  • Hi Rajesh,

    The LMX2581 has dual outputs and may be suited better for you application. However, if I understood your note, you wish to use the parallel input/divider/output structure of the LMK01801, is that correct?

    Gabe

  • Hi,


    Thanks for the recommendation. As per my application I want delayed clock(half cycle) for ADC & normal clock for track & hold amplifier. LMX2581 doesn't have any delay block for one channel.
    Is there any other device which has dual channel O/P with programmable delay on other channel.

    Note: In ADC12D1800 it has delay in the clock channels whether shall I use this delay block instead of LMK01801 clock switch delay.

    In my application I have two independent channels of analog to digital convertor thats why prefered LMK01801 switch which has two independent channels.

    Regards,

    Rajesh

  • Hi Rajesh,

    Is there a reason you wish to have delay on both channel paths? The delay on Bank B of the LMK01801 should allow you to delay/advance the signal with respect to A.

    Devices such as the LMK04906 can be used in distribution mode and each output channel features its own independent delay/divide blocks, but they are limited to one input.

    Gabe

  • Hi,


    Thanks for the recommendation, As per my application I have an 12 bit ADC for the RF signal digitalization in the range of 0.5GHz to 9GHz , In order to down convert  this in the front end of ADC I have track & hold amplifier. Both T/HA & ADC requires the sampling clock , I planned to provide 3.1GHz sampling clock to THA & 1.55GHz sampling clock to ADC(ADC will be operated in the DES mode). As per the above configuration I want 90 shift between 3.1GHz sampling clock & 1.55GHz clock. Now as per your suggession I planned to use LMX2581 which has two o/p channels. Now LMK01801 is not required. Instead I planned to use delay block which is available inside the ADC. I have one query on this ADC12D1800 what is the maximum possible delay we can intruduce on the samplinc clock on DES mode of operation.

    Regards,

    Rajesh

  • Hi Rajesh,

    The ADC section of the E2E forum will be better able to answer your question.

    Gabe