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CDCLVP111: CDCLVP111 input biasing

Part Number: CDCLVP111

I have customer with a couple questions on input biasing.

During system power up, there may be some duration where no clocks are driven.  So with traditional ac coupled biasing scheme the VID will be 0.

Will this cause oscillations or transitions?

Any suggestions to prevent oscillations during this time? 

Thanks,

Wade

  • Hi Wade,

    The input stage for most LMKxxxx clocking devices has built-in weak biasing that offsets the P and N side by few tens of mV. This is done to prevent 'chatter' on the inputs from causing noise amplification through the high gain input stages which could then result in a noisy output in the absence of any valid input clocks. In the absence of an internal offset to handle the scenario where the inputs are floating, care should be taken to include an external thevenin termination on the board to accomplish the same.

    Regards

    Arvind Sridhar

  • Thanks.

    I see that the CDCLVP111 also has small pullup and down resistors on CLK signals that will cover this case.

    Regards,

    Wade