• State Resolved
  • Locked Locked
  • Replies 7 replies
  • Answers 1 answer
  • Subscribers 21 subscribers
  • Views 1331 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LMK00301: VCCO voltage power-up requirement

Johnny Guo
Expert 4910 points
Part Number: LMK00301

Hi, Team,

Is there any VCCO voltage power-up requirement for LMK00301? Below is customer's test result in their system.

1.  Is there any risk for device work?

2.  What is the VCCO voltage threshold?

Thanks.

Johnny

  • 0
    TI__Expert 4910 points

    Anyone can help answer this question?

    Thanks.

  • 0
    TI__Mastermind 32575 points
    From the datasheet:
    10.1 Power Supply Sequencing
    When powering the Vcc and Vcco pins from separate supply rails, it is recommended for the supplies to reach their regulation point at approximately the same time while ramping up, or reach ground potential at the same time while ramping down. Using simultaneous or ratiometric power supply sequencing prevents internal current flow from Vcc to Vcco pins that could occur when Vcc is powered before Vcco.

    Can they share the VCC and VCCO power up waveforms together?
    What output mode are they using?
    Does the VCCO power up waveform cause any issue in their system?

    Alan
  • 0 in reply to Alan O
    TI__Expert 4910 points

    Alan,

    Please see below VCC and VCCO waveform. And currently customer does not find any issue in system test, just need to check the possible risk to device.

    Thanks.

    Johnny

  • 0 in reply to Johnny Guo
    TI__Mastermind 32575 points

    In the screenshot you sent, Vcc is clearly ramped sooner than Vcco, which would cause internal current flow from Vcc to Vcco pins until Vcco settles within the Vcco voltage tolerance (+/-5%) ~4 ms later.  

    Per the datasheet statement I sent earlier, it is recommended for Vcc and Vcco to be ramped simultaneously or ratiometrically to minimize this internal parasitic current flow from Vcc to Vcco and thus minimize risk to the device.

    Regards,
    Alan

  • 0 in reply to Alan O
    TI__Expert 4910 points

    Alan,

    This project is already in MP status, customer cannot change design anymore.

    So could you help confirm the risk for the internal current flow from Vcc to Vcco pins in this 4ms?

    Thanks.

    Johnny

  • 0 in reply to Johnny Guo
    TI__Mastermind 32575 points

    Johnny,

    We have a newer silicon revision (LMK00301A) that eliminates this parasitic current flow from Vcc to Vcco, and eliminates the power sequencing requirement and potential device risk.  I will contact you to get more details on your customer status, and close this thread.

    Regards,
    Alan