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LMK04826: LMK04826 Reset and loss of lock when cold

Derek Day
Prodigy 70 points
Part Number: LMK04826

Hi I have a board with an LMK04826 that is used with a 100MHz VCXO to provide a 125MHz clock to an Ethernet PHY.

When cold at -40C the LMK04826 loses lock and I start to see Ethernet instability.

Thinking the issue relates to a reset for the LMK04826 I investigated the connections of the reset pin.

I found that the pin is driven low by VHDL in an FPGA so it will be low when the FPGA is configured.

Looking at the LMK04826 datasheet I could not find any definative data stating how long the reset should be active for.

Anyone any ideas? Thought of investigation paths?


Regards Derek

  • 0
    TI__Mastermind 28540 points
    The spec for reset pin is on page 22, last item in the table. The reset pin should be active for 25 ns.

    Note, if you are concerned about noise on the RESET line, you can always make this pin an OUTPUT after/during initial programming.

    73,
    Timothy
  • 0 in reply to Timothy T
    Prodigy 70 points

    OK thanks Timothy, I had an old version of the datasheet without this information. Just for your information I found the route cause was the input supply voltage to the LMK04826 which due to greater current draw than expected was at the low end of the spec and fell below the spec values when cold. hence failure at cold.