Other Parts Discussed in Thread: ADC16DV160
Hi,
PLL(PART NO :LMK04808B) is tested with the following configurations.
Here PLL CLKout0 is used as source clock for ADC1(PART NO :ADC16DV160), PLL CLKout2 drives ADC2 of the same part.
ADC's sampling clock is same frequency as that of source clock.
(i)As per our requirement ADC1 is configured for 160 MHZ and ADC2 is configured for 144MHZ (Refer 3rd test case).
With the above configuration SNR degrades, in comparison with other frequency combination test cases.
(ii) With our default configuration(ADC1-160M, ADC2-144M), clock amplitude was reduced to 1200mVpp in ADC2 and tested(Refer 7th test case),
it was observed that ADC1 SNR is better compared to test case-3.
(iii) With our default configuration, clock type was changed to LVDS in ADC2 and tested(Refer 8th test case),
it was observed that ADC1 SNR is better compared to test case-3.
(iv) To idenitfy the source of problem to be ADC or PLL, ADC2 chip was power down and tested, even with it ADC1 SNR degrades with default configuration.
Then, we power downed clkout2, here ADC1 SNR improves(Refer 9th test case)
| Test case | Configuration | CLKout0(ADC1) | CLKout2(ADC2) |
| Frequency Variation | |||
| 1 | Frequency | 160 MHZ | 160 MHZ |
| Type | LVPECL, 2000mVp | LVPECL, 2000mVp | |
| SNR Observed | 57.01 | 55.14 | |
| 2 | Frequency | 144 MHZ | 144 MHZ |
| Type | LVPECL, 2000mVp | LVPECL, 2000mVp | |
| SNR Observed | 55.65 | 56.7 | |
| 3 | Frequency | 160 MHZ | 144 MHZ |
| Type | LVPECL, 2000mVp | LVPECL, 2000mVp | |
| SNR Observed | 51.84 | 55.87 | |
| 4 | Frequency | 144 MHZ | 160 MHZ |
| Type | LVPECL, 2000mVp | LVPECL, 2000mVp | |
| SNR Observed | 53.93 | 54.51 | |
| 5 | Frequency | 160MHz | 120 MHZ |
| Type | LVPECL, 2000mVp | LVPECL, 2000mVp | |
| SNR Observed | 59.54 | ||
| 6 | Frequency | 160MHz | 96 MHZ |
| Type | LVPECL, 2000mVp | LVPECL, 2000mVp | |
| SNR Observed | 56.74 | ||
| Clock amplitude variation in Clockout2 | |||
| 7 | Frequency | 160MHz | 144 MHZ |
| Type | LVPECL, 2000mVp | LVPECL, 1200mVp | |
| SNR Observed | 54.88 | ||
| Clock type Variation in Clockout2 | |||
| 8 | Frequency | 160MHz | 144 MHZ |
| Type | LVPECL, 2000mVp | LVDS | |
| SNR Observed | 56.8 | 54.44 | |
| Clockout2 Power down | |||
| 9 | Frequency | 160MHz | Power down |
| Type | LVPECL, 2000mVp | ||
| SNR Observed | 56.08 | ||
why ADC1 chip SNR varies with Clock frequency, amplitude and Clock type of ADC2?
