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LMK04803: Problem with Single PLL Mode.

Part Number: LMK04803

Hello,

At first, customer tested in Dual PLL mode  like as below with 10MHz Ref Clk to CLKin and 100MHz VCXO to OSCin.

And now, customer wants to use Single PLL mode with 10MHz Ref Clk to OSCin instead of  VCXO.

Can she use this Ref Clk to OSCin input?

To use 10MHz External Reference Clock to OSCin input, how customer can set Registers  and programming it?

Please let me get your advice ASAP.

Regards,

Nicky

  • That's correct.  The 10 MHz ref clock is connected to OSCin.  But sure at 10 MHz that the slew rate is met.

    As for programming the single PLL mode, the MODE register in R11[31:27] = 0x06 (PLL2, internal VCO).

    73,
    Timothy

  • Hi Timoty,

    10M ref clk slew rate spec is as below.

    - SRtpy. = △V / △t = 0.8Vdd / tr(tf) /= 2.64V / 4.5ns

    - SRmax. = △V / △t = 0.8Vdd / tr(tf) /= 2.64V / 10ns

    So, it meets OSCin slew rate (0.15~0.5V/ns).

    And customer test with external ref clk and LMK048003 clkout6 as OSCin input. 

    Attached figures are the output waveform of each ref clk.

    - PMC ext-lo sg on : External ref clk

    - PMC int-lo sg on : lmk04803 clkout6 

    Could you let me know why more noise is appeared when lmk04803 clkout6 is used? (PMC int-lo sg on)

    Also attached LMK048003 schematic, please review if there is any check point ?

    Regards,

    Nicky

    lmk04803.pdf

  • Hi Timothy,

    Could you let me get your answer ASAP?

    Customer also set as below, but still not working.

    Regards,

    Nicky

  • Reviewing the schematic.  Note that R322/C598/R323/C599 should be DNP.  These components are integrated.  Note the datasheet figure 20 illustrates this.

    I'm confused by the plots.  What is the significance of 1735 MHz?  The VCO is locked to 2000 MHz.

    I did some designs using the clock design tool.  When using your designed loop filter with 100 MHz reference, simulation is as below, very good performance (note, I am ignoring reference noise, if your reference is noisy and needs jitter cleaning, you may need to consider the dual loop):

    If I reduce the phase detector frequency to 10 MHz, the following results, note jitter increased from 116 fs to 255 fs.  PLL in-band noise also increased from below -120 dBc/Hz to above -120 dBc/Hz.  There is also some peaking from the loop filter.  This can be improved some by using the doubler and setting PLL2 R = 1 to achieve a 20 MHz phase detector frequency.

    Here I have re-designed the PLL2 loop filter with the 10 MHz reference.  Jitter improved from 255 fs to 207 fs.  While the PLL2 in-band phase noise is the same, the peaking associated with the unoptimized loop filter has been eliminated.  Perhaps you may try the filter below with

    Note, to do these simulations, I set the PLL1 filter type to "0 Hz."   You can load your 10 MHz reference phase noise for more accurate simulation, I just unchecked the VCXO as contributor and VCXO as visible (as VCXO is now the position of your XO).

    Note, it is possible to make these simulations using the Clock Architect software, but is a bit more effort for dual loop sims or dual loop devices as single loop sims.  Please refer to attached document for a guideline for simulation.  The instructions refer to LMK0482x but apply for LMK0480x.

    73,

    Timothy

    3125.Using Clock Architect for Dual Loop PLLs - in dual and single loop mode, 2017-03-21.pdf

    73,
    Timothy