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LMK04616: JITTER CALCULATION FOR LMK04616 JESD204B PLL

bharath
Intellectual 425 points
Part Number: LMK04616
Other Parts Discussed in Thread: LMK04828, ADS42JB69

Dear Sir,

I want to calculate the RMS jitter noise for LMK04616 Dual- PLL for my custom output frequency with Ref Clock soruce and VCXO.

In datasheet, phase noise is mentioned for only 122.88MHz o/p Freq. & Clock design tool also not supporting for this device.

please suggest, any clock design tool is available to calculate the RMS Jitter?

Clock design. :

1. 25MHz - TCXO

2. 100MHz - VCXO

3. PLL O/p Frequencies    

  - 60MHz - LVDS/LVPECL/HSDS

 -  240MHz - LVDS/LVPECL/HSDS

 - 100MHz - LVDS

 - 10MHz - LVDS

Regards,

K. Jaya Bharath Reddy

  • 0
    TI__Expert 8865 points
    Hi Jaya,

    The phase noise simulation tool for LMK04616 is not available yet.
    Please provide me the phase noise numbers for TCXO & VCXO. I can provide you the simulated phase noise & rms jitter for output clocks.

    Best regards
    Puneet
  • 0 in reply to Puneet Sareen
    Intellectual 425 points
    Dear Puneet,

    Please find Manu. part no for TCXO & VCXO used.

    TCXO - SiT5000AI-8C-33E0-25.000000

    VCXO - CVHD-950X-100.000

    Required output frequencies for LMK04616 are,

    Required Device Clocks -

    1. 60MHz - LVDS/LVPECL mode

    2. 240MHz - LVDS/LVPECL mode

    3. 100MHz - LVDS mode

    4. 200MHz - LVDS mode

    Required Sysref clocks -

    1. 10MHz - LVDS clock\



    Regards,
    K. Jaya Bharath Reddy
  • 0 in reply to bharath
    TI__Expert 8865 points

    Hi Bharat

    Here are the simulation numbers:

    240MHz Phase noise

    Hz      dBc/Hz

    1k          -125

    10k        -135.3

    100k      -143.5

    1M          -151.5

    10M       -162.6

    rms jitter (10K-20MHz): 58fs

    for other frequencies, here are the rms jitter numbers:

    200MHz: 58fs

    100MHz: 73fs

    60MHz: 94fs

    Best regards

    Puneet

  • 0 in reply to Puneet Sareen
    Intellectual 425 points
    Hi puneet,

    Thanks for your information.

    Regards,
    Jaya Bharath reddy
  • 0 in reply to bharath
    Intellectual 425 points
    Dear Puneet,

    Currently in our design i am using LMK04828 PLL. My plan is not to disturb the present configuration.

    My sampling clock requirement for ADS42JB69 is 60Msps. With VCO Frequency of 2400MHz i can't able to generate 60MHz since required clock divider value is 40.

    Please suggest whether i can use Clock divider between LMK04828 & ADC. Please suggest any low jitter Clock divider from TI/Other manufactures like IDT, etc,.

    provide RMS jitter values for LMK04828 for below mentioned outputs,

    TCXO - SiT5000AI-8C-33E0-25.000000

    VCXO - CVHD-950X-100.000

    Required output frequencies for LMK04828 are,

    Required Device Clocks -

    1. 120MHz - LVDS/LVPECL mode - Clock Divider to be used to generate 60MHz clock

    2. 240MHz - LVDS/LVPECL mode

    3. 100MHz - LVDS mode

    4. 200MHz - LVDS mode

    Required Sysref clocks -

    1. 10MHz - LVDS clock

    Regards,
    K. Jaya Bharath Reddy