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25Hz Clock buffer with programable delay and low output jitter

user4957257
Prodigy 40 points
Other Parts Discussed in Thread: LMK04828

Hi,

    I have an design requirement of distribute an 25Hz clock singal to at least 4 outputs with programable output delay and very low output jitters,

I didn't find any proper clock buffer on TI's website, so I wonder if there are any device you suggest can solved my problems?

  • 0
    TI__Genius 9920 points

    Hi,
    What's the 25 Hz signal type ? LVCMOS , LVDS or sin wave ......?
    How much delay range and step does system require?
    What's the output jitter spec.?
    I guess a FPGA could implement them.

    Regards,
    Shawn

  • 0 in reply to Shawn Han
    Prodigy 40 points
    Hi Shawn：
    Thinks for your reply, our customer have not provide us an detail requirment yet,it seems that the the 25Hz singal is LVCOMS Type.
    I have already think about the implement them with FPGA,while it's difficult to get a low output jitter picosecond ,so maybe I need another jitter cleaner device to get a lower jitter?
  • 0 in reply to user4957257
    TI__Genius 9920 points

    Hi,

    Current TI clock jitter cleaner has 200fs (Digital Synchronizer: LMK05x28, coming soon in next several months, it can support 25Hz input and output), 100fs (Analog dual PLL jitter cleaner: LMK04828, it can't support 25 Hz) level, next generation jitter cleaner would reach 60fs rms jitter (12kHz~20MHz ). Customer could wait for LMK05128.

    Regards,

    Shawn