Hi,
I'm designing a clock fanout circuit (125MHz) for an ASIC which accepts LVDS or LVPECL levels but with a stringent differential voltage swing requirement of 500 - 900mV at its pins. In the datasheet (Page 7) of CDCP1803, the field "Output voltage swing between Y and Y" has a minimum value of 500mV but there is no typical or maximum value given. Power supply is 3.3V.
Is there a reason for this? Or is there a way to calculate the typical and maximum values from the datasheet?
Fig. 3 shows the output voltage swing over frequency but this is only at 25°C (ambient). At 125MHz, this amounts to approx. 825mV. Is this the maximum value?
Thanks!