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TLC555: minimum width of trigger pulse

Part Number: TLC555
Other Parts Discussed in Thread: NE555

Dear all,

One of my customer has the follwing request:

When using the TLC555 in monostable mode as shown in the data sheet to stretch a pulse we are expecting an output pulse of 143 mS. (R = 130 K, C = 1 u, Vcc = 3.3 V).
The trigger input is a  ve pulse of 500 nS and P.R.F of 20 Hz and amplitude 3.3 V.
On the PCB containing the 555 Timer we found that the output pulse was not as expected. The output pulse on pin 3 of the timer was found to be a mirror of the trigger pulse on pin 2 rather than the 143 mS pulse we expected.
A simulation of the circuit using simetrix software suggest that there is a minimum trigger pulse width of 6 uS below which the 555 does not function as a pulse stretching IC. This ties in with what has been seen on 2 separate PCBs. Can it be confirmed that this is the expected behaviour of the IC for the conditions?

regards,

Domenico

  • Domenyko,

    Are you saying that the input trigger is low (0V) for only 500ns and high the rest of the time; output is high for only 500ns and low the rest of the time? Check pin 6 waveform, maybe 1uF cap isn't really connected.

    I'd prefer a >=1us trigger pulse

    Here is sample trigger to output time charts for trigger low voltage.

  • Hi Ron,

    "input trigger is low (0V) for only 500ns and high the rest of the time; output is high for only 500ns and low the rest of the time?"

    Your understanding of the input trigger is correct. However the output is the opposite. That is to say that the Output is low for the 500 ns that the trigger pulse is also low then is high at all other times.

    We have confirmed that the capacitor is connected correctly and have been able to model the PCB behaviour in a simulation and the same results are produced.

    Is this something you have seen before?

    In relation to graphs we have a Vcc of 3.3 V so the top right is the most applicable however I am not quite sure what the graph shows?

    Thanks in Advance,
    Darren
  • Darren,

    The output could be trigger signal inverted, but output can't be same as trigger. I have not seen that.

    Here is my simulation (transient 1us).

    TLC555 one shot.TSC

    Another potential problem is that trigger period is 50ms and one shot is 143ms. How would you like that to work? 

    Top right chart is closest??? That is NE555, isn't the part TLC555? The chart is time delay from trigger low edge to output high edge.

  • Hi Darren, I haven’t heard back from you, I’m assuming you were able to resolve your issue. If not, just post a reply below (or create a new thread if the thread has locked due to time-out) – thanks, Ron.
  • Hi Ron,

    Apologies for the slow reply.

    We did indeed solve this problem.

    In short the issue was with the logic State on the internal flip flop inputs.

    We found that with out input pulse we reached a stage where both S and R were logic 1 which meant the Flip Flop was locked.

    We added additional circuitry to the trgger signal  (to Invert and slow) and found this corrected the issue.

    Regards

    Darren