LMK04828BEVM: Could you kindly help to suggest about the configuration, how to config the output is 2.5G?

Hello Lian
You will have to use BYPASS divider from DCLKoutX_MUX in this case.
You will not get a good quality 2.5GHz output with 122.88MHz input. PLL2 PFD runs at 160kHz and the PLL2 bandwidth needs to be very low (~16kHz) in this case. You will have to change the PLL2 filter components in this case to make the PLL2 stable. Please use Clock Design Tool or Webbench tool from ti.com.
Is your input frequency fixed to 122.88MHz or it can be 100 MHz instead? In this case you can use 100MHz VCXO and have a very good quality 2.5GHz output.

Best regards
Puneet