LMK04828: latch up at I/O PINs

Lilian Chang

Intellectual 1555 points

Part Number: LMK04828

Hi Team,

There is 1.8V voltage at below I/O pins before device power up, if there is any risk to cause latch up?

Pin # 31(I/O Status_LD2)、48(I/O Status_LD2)、18(I CS)、19(I SCK)、20(I/O SDIO)、5 (I/O RESET/GPO)、

60/61/62/63 (AC coupled )

over 6 years ago

0 Simon Damphousse over 6 years ago

TI__Expert 5370 points

Dear Lilian,

thank you for your interest in LMK04828. I do not see risk of latchup on these pins. no problems.

The SPI input at 1.8 V is fine.

The digital output 31 and 48 are also fine at 1.8V. I am not sure why you would force 1.8 V on these output but likely transitory setup.

Regards, Simon.

0 Lilian Chang over 6 years ago in reply to Simon Damphousse

TI__Intellectual 1555 points

Hi Simon,

Thanks for your reply.
This is FPGA bug I think. Before our device be powered up, there will be a 1.8V voltage for 10us.

0 Simon Damphousse over 6 years ago in reply to Lilian Chang

TI__Expert 5370 points

understood, Let me know if you have further questions of issues, happy to help, regards, Simon.

Clock & timing

Clock & timing forum

LMK04828: latch up at I/O PINs