CDCE913-Q1: measured spread spectrum waveform is different from datasheet

Hi
This is because you are using the PLL in the fractional mode and enabling the SSC. The plots in the datasheet are with the integer PLL settings. Try to use a XO frequency which has an integer relation to the output frequency. We have another device CDCI6214 which is more flexible in choosing the PLL parameters to establish the integer frequency relationship from input frequency to the output. Dont hesitate to contact me for further assistance.
Best regards
Puneet

Hi Puneet,

Thank you for your advice.
I want to check my understanding.
You mentioned that I can get spread spectrum waveform like Figure 23 if I set 'fvco' value as integer.
Can I get the intended spread spectrum waveform with the following condition?

>Condition
Target frequency: 6.8MHz
M: 100, N: 1700, Pdiv: 20

In addition, CDCI6214 is catalog rating.
Are there any better devices for automotive rating?

Best regards,

Hello,
Yes, for the target frequency of 6.8MHz this configuration should work with CDCE913-Q1.
CDCI6214-Q1 will be released later this year.
Best regards
Puneet

Hi Puneet,

We could not get the waveform like Figure 23 but like our waveform posted at first.
We could not get it in spite of the Condition ---> Target frequency: 6.8MHz [M: 100, N: 1700, Pdiv: 20].

What is wrong do you think?
What information do you need to think the reason?

Best regards,

Hi Puneet,

Here is register map.

Clock Pro picture.pdf

We only changed following registers. (the other are default)

Reg2 : 0xB4

Reg3 : 0x14

Reg18: 0x08

Reg20: 0x6D

Reg22: 0x80

Reg24: 0x6A

Reg25: 0x40

Reg26: 0x02

Reg27: 0x21

Best regards,

Hello

Thanks for sharing the data. I checked the SSC performance with those settings. Please see the attached plots. The measurements are performed with the same settings like the picture in the datasheet.

I would recommend CDCI6214 if better SSC performance is required. The automotive version will be released mid of this year. The performance can be evaluated using the industrial version and the EVM is orderable.

Best regards

Puneet

Presentation1.pdf

Hi Puneet,

Thank you for your measurements and supports, but your measured waveform is the same as mine. (Just scale is different.)

SSC measurement.pdf

Does your waveform says that the frequency is changing not discretely but continuously to time?

*I read ... Data sheet says that the frequency will change like triangle wave to time. 

It looks that the frequency changes to fixed frequency discretely to time.

My understanding is wrong? Is this waveform is correct operation for CDCE913?

Best regards,

I think the difference in the frequency spectrum plots appear may be caused by differences in the spectrum analyzer resolution BW, and video BW, and sweep rate between the datasheet and your/Puneet's measurements.

Alan

Hi Alan,

Thank you for your response.
I will check with re-setted measurements.

Could I check you about my understanding?
>Check 1
Does SSC make the frequency change not discretely but continuously to time?
>Check 2
Did I just mistake about measurement setting? Did this device work correctly?

Best regards,

1. The SSC frequency modulation is continuous in time.

2. I think so.  Besides adjusting the RBW, you can also try using max-hold mode to see the SSC spectrum envelope. 

Alan

Hi Alan,

Thank you for your always help. But some issues has not resolved yet.

Please look below,

waveform measurements.pdf

1)  We measured with analyzer setting changed.

We think that the analyzer setting has very little to do with test results.

The test result with RBW:10kHz and VBW:100kHz just became gradual form.

2)  COMPE's SSC waveform

Please looke at attached file that COMPE's waveform.

No.1 and 2 is the same setting but the time measured is different. This COMPE's SSC does not fix specific frequency but drastic changes continuously.

On the other hands, TI's SSC does not look like changing continuously. And this SSC fix the frequency discretely (for example, 6.76MHz, 6.84MHz).

■QUESTION 1; Don't we mistake register setting?

■QUESTION 2; Must we send specific signal to this device? (We think that data sheet does not say this.)

■QUESTION 3; Did it is wrong that we selected 8MHz Xtal?

3)  SSC: ±0.25%

■QUESTION 4; What is the mean of '±0.25%'?

At the actual waveform, both side peak are 6.8396MHz and 6.7598MHz to the center '6.8MHz'. This means that 6.8MHz ±40kHz --> ±0.558% not 0.25%.

Best regards,

In discussing with Puneet, the 0.25% spread will not have the same SSC profile as the 2% spread shown in the datasheet. Also, the VCO frequency having a non-integer relationship with the XTAL input frequency will also affect the SSC profile. So, the customer's result is expected given the differences in the PLL/SSC configuration and frequency plan.

I suggest to modify the Input clock frequency and VCO frequency to get an integer relatonship and use 2% spread to see if that improves the result. Otherwise, please propose the CDCI6214 (which Puneets suggested previously) which should not have this limitation.

Alan

Hi Alan,

Thank you for your answer.

Please see attached file of my post on Feb 8, 2018 1:27 PM.
In this test, we used integer setting.
>Condition
Target frequency: 6.8MHz
Crystal; 8MHz, M: 100, N: 1700, Pdiv: 20, SSC: 2%

We had already tested with the condition of integer crystal, integer VCO and 2% SSC.
However, we could not get expected result...
■QUESTION 5,
What is the cause? Why does some peak waveform appear with SSC?

■QUESTION 6,
Could you answer about QUESTION 4 at previous post?

■QUESTION 7,
If we use CDCI6214, will these problem is resolved?

Best regards,

5. I was told there are 8 frequency steps going up and down, but the SSC logic is in the PLL feedback path and getting smoothened by the PLL bandwidth.
6. Yes, the % is the modulation amount or depth. +/-2% center spread on 6.8 MHz is +/-136 kHz.
7. That was Puneet's suggestion. I defer to him since he has more experience with these SSC clock-gen devices.

Alan

Hi Alan

>about 5,
You mean that
if we set larger fvco value, we can get smoother spread spectrum waveform?
Could you teach us how to get smoother spectrum waveform for 6.8MHz output?

In addition, could you teach us the register configuration of Figure 23?

>about 6,
I tought like your answer, but, like QUESTION 4, side peak are 6.8396MHz and 6.7598MHz to the center '6.8MHz'. This means that 6.8MHz ±40kHz --> ±0.558% not 0.25%.
How do you explain of this result?

Best regards,

Hello
I think the behavior is due to low frequency output. We have those frequency steps applied in the PLL loop, at VCO frequency, when the output frequency is divided down so much, the frequency steps are accumulated and effectively you see less frequency steps. Have you checked by running the output at higher frequency?
Our new device CDCI6214 should be better as the SSC logic is implemented in the output path( FOD )and the frequency sweep is very fine with the fractional divider.
Best regards
Puneet

Hi Puneet,

Thank you for your answer. However, I cannot understand the reason why we can get smoothly waveform with higher frequency. or the reason why we cannot get smoothly wavefrom with lower frequency...
Could you explain this reason?

In order to compare our result and high frequency settings,
could you teach us the register configuration of Figure 23?

Could you teach about previous post?
"I tought like your answer, but, like QUESTION 4, side peak are 6.8396MHz and 6.7598MHz to the center '6.8MHz'. This means that 6.8MHz ±40kHz --> ±0.558% not 0.25%. How do you explain of this result?"

In order to recommend CDCI6214 for my customer, could you provide me with the test result under customer settings?
>customer settings
XTAL: 8MHz, output frequency: 6.78MHz, SSC: ±0.25% or ±2%

Best regards,

Hi Puneet,

Could you support my post at Feb 22, 2018 7:36 AM?

Best regards,

Hello Takao-san
Let me reproduce your spread results for CDCE913 in our Lab. I will also send you a plot from CDCI6214 today. Thanks for having patience.
Best regards
Puneet

Hello Puneet,

Than you very much for your supports.
I am looking forward hearing from you.

Best regards,
Takao Yamamoto

Hello Takao-san

Thanks for having patience. Please find attached some plots from CDCI6214 measurements. While running at 6.78MHz clock, what is your emission target? I would expect that you might be interested in peak radiations at higher order harmonics of 6.78MHz!

Regarding your question on the CDCE913 SSC spread, its difficult to say from your plot. spread is usually measured from the 3dB points. I would propose to change the output dividers to run the output clock at higher frequency and then check the actual spread.

Best regards

Puneet

CDCI6214_SSC_6p78MHz.pdf

Hello Puneet,

Thank you for your deeply support. And your test reult is very helpful for us.

But some question is not clearly resolved yet.

>QUESTION 1,

Could you re-test CDCI6214 by SPAN=300kHz?

Maybe, I imagine that spectrum waveform will be non-smooth form like CDCE913's.

Cannot TI's IC output SSC waveform smoothly(not skip) like previous competitor waveform?

Here is precvious competitor waveform at page3-5. 2514.waveform measurements.pdf

Could you explain the reason of these difference?

>QUESTION 2,

About ±○○% SSC specification, what is the definition of this specification?

The tested spectrum waveform looks like having wider SSC range than setting percentage.

And I can say about this to both CDCE913's and CDCI6214's spread waveform.

>QUESTION 3,

What is 'spread is usually measured from the 3dB points'?

I cannot understand about 3dB points.

>QUESTION 4,

What is 'change the output dividers to run the output clock at higher frequency'?

Now, we set the output waveform 6.8MHz or 6.78MHz.

Do you mean that we should set higher output frequency over 6.8MHz or 6.78MHz?

If this is true, Is setting lower output frequency the root cause why we cannnot get smooth SSC?

Best regards,

Takao Yamamoto

Hello TI team,

Could anyone support our questions?

Best regrads,

Hello Takao-san,
Thanks for having patience. I will redo the measurements with SPAN=300kHz and send it to you as soon as possible.
Here are my comments to your questions:
>QUESTION 1
A: The spectrlal waveform depends on the SSC implementation. Those two of our devices does not have randomization between the frequency steps, that is why when you divide down the output clock to such a low frequency, you see accumulation of the frequency steps and spectral waveform does not look good. The use cases i had seen for SSC are mainly higher frequencies. We will improve the performance in the new devices we release in future.
>QUESTION 2,
SSC spread depends on how you measure it. Best would be to measure in time domain. The actual spreads in our devices are not more that what is specified.
>QUESTION 3,
By applying the SSC, fundamental power is spread over +/- x%. The SSC spread is taken from that power level to the frequency where power level drops by 3dB. Have you checked the spread in time domain?
>QUESTION 4,
Yes, that is what i meant. I think your observed waveforms are only at low frequency. Have you checked the SSC spectral waveforms at higher output frequencies?