LMX2594: change frequency fast with VCO calibration full assistant

I expect lock time is much less but it took 500us. this is a frequency change from 11.5G to 7.5G with VCO calibration full assistant

can you point out what could be wrong?

Sheng,

In addition to Simon's response and our phone conversation, we can follow up next week.

I think the first should be to separate out what is VCO calibration time from what is PLL settling time. Some things to try are:

1. Change charge pump current to test Loop Dynamics:
Lower charge pump current should be lower loop bandwidth, and longer lock. Opposite for high charge pump current. In your bottom picture, see what impact it has. If it has no impact, this implies VCO calibration, otherwise it implies PLL loop dynamics.

2. Deal with Fraction and Reset:
Consider trying an integer channel to get the fraction out of the equation. I don't think it is, but coudl be. You could also set MASH_RST_N=0 and see what this impacts.

Regards,
Dean

Hi Dean and Simon
in my set up, I have an external phase detector(a mixer) that beats LMX2594 output at its final frequency(7500.5MHz, after a frequency change from 11500.5MHz) with a Keysight synthesizer that is set to 7500.5MHz. both LMX2594 and keysight synthesizer are locked to the seame 10MHz reference

this is a standard way of measuring PLL lock time with a frequency step. in order to verify this setup is doing the job, I have logged time between last CSB rising edge and MUXout lock detector. these 2 agrees well since the lock time is excessively long

I intended to use 10MHz x2=20MHz as my PFD, fractional mode, VCO calibration full assistant to measure lock time for a frequency jump from 11500.5MHz to 7500.5MHz.

I noticed register R8, bit 11, if I set this bit =1, I can not lock to the desirable frequency of 7500.5M

ALSO, with a charge pump current from 15mA to 6mA, lock time increased a little bit but the dominant long lock time is still there

see do difference between an integer mode and a fractional mode and this lock time looks like random

Mash_RST_N need to be 1, otherwise it locks to a nearest integer frequency

VCO_phase_sync=0

I think at this time, I think the best thing to do is let me duplicate what you can do with this task and we may able to figure out why

the test would be jump freq from 11500.5M to 7.5005MHz, with PFD 20M, internal x2 on, use full VCO calibration assistant, and measure lock time.

in all my measurement, I have a loop BW=200kHz

Sheng,

I'll follow this up tomorrow with a call.

The fact that setting R8[11]=1 causes a problem with locking suggests that you are programming in the wrong VCO_CAPCTRL value and perhaps giving the VCO invalid calibration settings.
Also, it looks like you are programming R0 with FCAL_EN=1. If you do this, it will activate the VCO calibration, EVEN if you have the VCO_CAPCTRL, VCO_DACISET, and VCO_SEL all forced. If the value is forced and you tell the device to calibrate, it will first calibrate and then overwrite the values with the forced values. Also, it seems that many of these registers are not necessary to program to switch channels such as fractional denomninator and also the VCO_DACISET_FORCE and the other force bits.

Regards,
Dean