LMK04828: LVDS Output Model

Mark Guastaferro

Part Number: LMK04828

Can you provide a simple model of the LVDS output stage for the CLK/SCLK outputs? I want to see how the output levels and common mode voltage are affected by terminating the output with a thevenin termination as we do on some of our ADC interfaces.

I made a simple TINA model based on how I assume the LVDS output is driven (current steering H-bridge with a Vcm loop), but the results don't align with actual board measurements.

over 6 years ago

0 Puneet Sareen over 6 years ago

TI__Expert 8865 points

Hi Mark
DId you try IBIS model?
Best regards
Puneet

0 Mark Guastaferro over 6 years ago in reply to Puneet Sareen

TI__Genius 11095 points

Unfortunately, I don't have a tool to run the IBIS model. I've looked at the text of the model, and I'm not sure if it will give me what I'm interested in. Maybe you can run it for me.

Basically, each side of the LVDS output is terminated with a 182 ohm pull-up to 3.3V plus a 68 ohm pull-down to ground (looks like 50 ohm load with Vcm = 0.9V). This is DC-coupled to the ADC SYSREF input. What would the expected Voh/ Vil levels at the termination ignoring the ADC load for now (should be high impedance anyway)?

0 Shawn Han over 6 years ago in reply to Mark Guastaferro

TI__Genius 9920 points

Hi Mark,

Simulation without considering transmission line and ADC input impedance, Vil is around 0.70V, Vih is around 1.25V.

p.s. For IBIS model simulation, you could use HyperLynx SI from Mentor Graphics Corp. with license.

Regards,
Shawn

0 Mark Guastaferro over 6 years ago in reply to Shawn Han

TI__Genius 11095 points

Hi Shawn,

Thanks for running this. When I tested this set-up on an LMK04828 eval board, I get Voh = 1.25V, and Vol = 0.82V. High level aligns, but low side is a bit off.

0 Shawn Han over 6 years ago in reply to Mark Guastaferro

TI__Genius 9920 points

Hi Mark,
Thanks for your measurement. Make sure you had remove the bias resistor 560 Ohm on the LVDS output of LMK04828 EVM.
Vod= 1.25 - 0.82 = 0.43 (V)
It is a reasonable LVDS output amplitude.
Please refer to your real test result.

Regards,
Shawn

0 Mark Guastaferro over 6 years ago in reply to Shawn Han

TI__Genius 11095 points

Thanks Shawn,
I actually used SDCLKout3 for my experiment. Is only has 240 ohm pull down resistors and no differential termination resistor (for LVPECL I suppose). I modified these to 68 ohms and then added the 182 ohm pull-ups to each side. Then I used TICS Pro to modify this output's mode and frequency to get the measurements. I measured the logic levels on the LMK side of the output coupling caps with no load on the other side of the caps.

0 Shawn Han over 6 years ago in reply to Mark Guastaferro

TI__Genius 9920 points

No problem for your measurement.

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LMK04828: LVDS Output Model