CDCI6214: jitter for each output

Saki

Intellectual 890 points

Part Number: CDCI6214

Hi team,

Could you provide the Maximum value of RMS phase jitter for each output about two case ?

My customer is thinking to use this for their next project.

[ Condition ]

■Input

CLK 27MHz(OSC※)

Case1 Xtal

Case2 Xtal oscillator

Phase noise (dBc / Hz)

Fout ± 1kHz(Typ.) -145 -140 -135 -126 -119

Fout ±100kHz(Typ.) -160 -156 -154 -151 -146

■Output CLK

1. LVDS 148.5MHz
2. LVDS 148.3516MHz

3. LVDS 300MHz

4. LVDS 100MHz

5. LVCMOS 27MHz

Of course, I saw the D/S P.12 but it seems to depend on condition.

Best Regards,

Saki

(dBc / Hz)

> > > Fout ± 1kHz(Typ.) -145 -140 -135 -126 -119

> > > Fout±100kHz(Typ.) -160 -156 -154 -151 -146

over 5 years ago

0 Simon Damphousse over 5 years ago

TI__Expert 5370 points

Dear Saki,

Thank you for reaching out.

We would not be able to provide a MAXIMUM unless we screen each and every device for this specifications. This is expensive and even more so for integrated noise. We may be able to provide typical values.

Regards, Simon.

0 Lane Boyd over 5 years ago in reply to Simon Damphousse

TI__Genius 16845 points

Hi Saki,

Are you generating clocks for a video application, such as PAL/NTSC switching? If so, CDCI6214 may not support this application; CDCI6214 fractional output divider is designed with a fixed denominator, and cannot exactly hit a 1000/1001 divide ratio.

I can provide a typical measurement for your use case tomorrow.

Kind regards,
Lane

0 Saki over 5 years ago in reply to Lane Boyd

TI__Intellectual 890 points

Hi Lane-san,

Thanks for your reply!

Could you please provide typical measurement ?

Best Regards,
Saki

0 Shawn Han over 5 years ago in reply to Saki

TI__Genius 9920 points

Hi Saki,
The problem is CDCI6214 can't achieve below frequencies together with divided by exact 1.001 .
1. LVDS 148.5MHz
2. LVDS 148.3516...MHz (= 148.5/1.001)
Will you switch pal/ntsc in your system?

Regards,
Shawn

0 Saki over 5 years ago in reply to Shawn Han

TI__Intellectual 890 points

This is setting of CDCI6214.

27MHz ref clock --> 148.5MHz、148.351MHz output at a time.

Could you pls provide the jitter characteristic for each output?

0 Shawn Han over 5 years ago in reply to Saki

TI__Genius 9920 points

Hi Saki,
As I mentioned, there are frequency offset from CDCM6214 outputs in this fractional setting.
148.500002MHz vs. target 148.5 MHz
148.351638 MHz vs. target 148.5/1.001 MHz
Does customer accept this frequency error?

Regards,
Shawn

0 Saki over 5 years ago in reply to Shawn Han

TI__Intellectual 890 points

Hi Shawn-san,

Yes, they can accept it.

Best Regards,

Saki

0 Shawn Han over 5 years ago in reply to Saki

TI__Genius 9920 points

Got it. AE would measure them as your requested.
Any output jitter requirements or phase noise target customer needed?
CDCI6214 loop filter may be optimized according to performance target.

Clock & timing

Clock & timing forum

CDCI6214: jitter for each output