LMK04832: Exit based on DLD

Hi Kudo,
Could you monitor Holdover status and DLD staus on pins?
It is possible lock status is not stable, enter holdover again. Repeat lock-unlock-enter holdover-exit holdover.
If it is such situation, please try a larger HOLDOVER_DLD_CNT.

Regards,
Shawn

Exit by LOS provides and simple way to exit holdover. When the input signal is detected by LOS, device will exit holdover and lock.

When exiting by DLD, the register fields PLL1_WND_SIZE and the HOLDOVER_DLD_CNT work together to set a required ppm accuracy of the reference clock to exit holdover Setting larger PLL1_WND_SIZE and smaller HOLDOVER_DLD_CNT will result in a holdover that is easier to exit as a wider ppm error is acceptable. Exiting holdover by DLD exit occurs when the phase of the divided reference (output from PLL1 R) aligns (or briefly crosses) with the phase from the divided feedback (output from PLL1 N) within the settings of PLL1_WND_SIZE and HOLDOVER_DLD_CNT. When using this exit by DLD, it is possible that in holdover a reference is present and 180 degrees out of phase with the feedback (holdover) clock. If the reference frequency has very low PPM error to the holdover frequency, it can take long time for the phase of PLL1 R and PLL1 N to drift and cross so the device can confirm an accurate reference and exit holdover. So holdover exit time could be a minute or more. For reference with some ppm error, then the drift from 180 degrees to 0 degrees is much faster and holdover will exit very quickly.

The TICS Pro LMK04832 tool will calculate the required PPM needed for holdover exit given the settings programmed under 'Phase Detector Holdover exit Conditions' on the Holdover tab.

You can observe what is happening by setting the PLL1 R/2 and PLL1 N/2 debugging output on Status_LD1 and Status_LD2 pins and probing with oscilloscope.

73,
Timothy