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LMX2572EVM: LMX2572EVM

Part Number: LMX2572EVM
Other Parts Discussed in Thread: LMX2572, PLLATINUMSIM-SW, LMX2594

 Hi,

I am using LMX2572 Evaluation board. Below are issues faced

Our application is to run the evaluation board in Sawtooth Auto Ramp mode with >1ms. We are sweeping 5800-5900MHz for a Radar application.

The sweep is not happening properly, attached is the ramp setting screen shot for reference

1. The PLL is not stable with the loop filter values of 1MHz:

   C1_LF: 15 pF

C2_LF: 450 pF

R2_LF: 2.5 k

R3_LF: 0

C3_LF: DNP (open)

R4_LF: 0

C4_LF: DNP (open)

 Apart from this,

R16, R19, R20: 0 Ohms (short)

We have tried changing the loop filter values, the PLL is not stable even in higher bandwidth.

I need solution for stable PLL output and sweep from 5800-5900MHz,in sawtooth ramp mode ASAP.

Regards,

Suresh

  • Hi Suresh,

    Your loop filter capacitor C1 is too small. I am sorry that we did not make this clear in the current datasheet. We are in the process of revising the datasheet to highlight this requirement. We recommend to put at least 1.5nF cap close to the Vtune input pin. So if it is a second order filter, then C1 should be placed closed to the Vtune pin.
    Your ramp is between 5800 and 5875MHz, we suggest make the limit a bit higher than these frequencies. For example, ramp limit High = 6000MHz; ramp limit low = 5700MHz. Furthermore, try doing a calibration-free ramp by making the threshold greater than the ramp range. So make threshold = 100MHz.
    Also make sure your fpd is less than or equal to 100MHz. This is make ramping more stable.
  •  Hi Noel Fung,

    I tried changing the C1 value to 1.5nF and there was some improvement in the locking process, still the output is not stable at lower span of 500KHz and below.

    The  ramp settings was done as per your suggestion with some margin  on the Threshold. The frequency sweep has now totally stopped.

    Earlier there was some kind of sweep happening.  

    Has the C1 cap has changed the characteristic , by increasing the lock time  due which sweep is not happening.

    Earlier we had an eval board on loan in which with same loop filter as mentioned earlier has been working where in sweep was happening.

    This issue needs to be resolved to proceed further with the TI LMX2572 solution ASAP

    The below pic shows that the sweep is not happening as per the ramp settings.

    Regards,

    Suresh

  • Hi Suresh,

    First of all, make sure the PLL is stable in the steady state. Use PLL Sim (www.ti.com/tool/pllatinumsim-sw) to design a proper loop filter. Keep in mind that the fpd should be <=100MHz in ramp mode.

    Set the ramp limit range greater than the ramp range.

    if it is still fail, can you confirm you can successfully repeat the calibration-free ramping example as shown in the EVM User's guide? If the result is positive, can you can modify the setting to make a sawtooth ramp?

  • Hi Neol Fung,

    Thanks for your response. 
    I was trying to stabilize the PLL using the PLLatinum Sim software and simulate the 2nd order and 3rd order 
    Loop Filter. 
    With the C1 Value high the loop bandwidth values in AUTO mode with FPD at 100MHz. the maximum 
    bandwidth achieved was around 200KHz  with lock time of 137uS. If the C1 value is reduced the loop bandwidth.
    As per your recommendation the C1 value has been fixed to 1.5nF. 
    If my understanding is right the damping of the C1 cap has an impact on the loop bandwidth and lock time.
    Please let me know how to proceed further in this regard.
    I have one of the 3rd order loop filter calculation for your reference, where the design target was 500KHz  but the actual it shows 
    198 KHz. The plot shows around 1MHz  which one is the correct ?
    On the Ramp with your recommendations the sweep was not happening, this might be due to large lock time 
     
    can be increased till 1MHz, but the stability is not there 
    Regards
  • Suresh,

    For the tool, the intention is to put the 1.5 nF for the "Min High Order Cap" box.  When this is done, PLLatinum sim will adjust the loop bandwidth down to maintain this value.  When this is done, it will maintain the same phase margin and damping factor.

    In the design above, it seems that you have set this to 0, and you are getting 160 pF for C3.  This will work but there will be degradation in the VCO phase noise on the order of about 10 dB.  PLLatinum Sim does not model this effect.  However, it mentions it in the design tip and it seems like it is highlighting the C3 component.

    The design screen shows about 200 kHz loop bandwidth, but the plot shows around 100 kHz and certainly not 1 MHz.  

    If you want faster lock time and deal with this constraint, try the following:

    1.  Design 2nd order filter.

    2.  Use maximum charge pump gain.

    3.  Design for lower phase margin, around 48 degrees.  This gives faster lock time and also larger high order capacitor value.

    Regards,

    Dean

  • Thanks Dean for the input

    1. I designed 2nd order loop filter fixing C1 1.5nF  and phase margin of 48 deg.  The loop bandwidth achieved was 234 KHz with lock time of 154.3 ns including calibration.
      1. The output spectrum was not stable at 5.8GHz at span of 500KHz 
    2. The Ramp out put with the recommend setting with 90MHz threshold with around 234KHz bandwidth the spectrum output is not as per requirement. I need to load the software every time for it to ramp, once the ramp is disabled and enabled again it does not work even after several repeats.
    3. I looking for quick solution from  TI in this case as  recommendation of this device to replace Analog devices chip set as LMX2572 has built in VCO and things are not happening as expected, we purchased evaluation board to achieve faster results. There is very less of documentation and application notes with respect to this device compared to LMX2594.
    4. We are LMX 2572 for  FMCW Radar application in Sawtooth Ramp in our application at 5.8GHz band.

  • Suresh,
    Looking at your loop filter on PLLatinum sim picture, it is theoretically stable, but it's not clear from your post if it is for the steady state. The plot shows smearing that looks like 5000 to 5875 MHz, which looks like your ramping range. So it's not clear to me if ramping is on or off.

    For ramping mode, realize that for this device, the device might not be able to go 30 MHz without re-calibrating the VCO; this is sort of marginal and you might need to make this more like re-calibrating every 10 MHz for something that is more robust for process and temperature (although there is no datasheet guarantee on how far the VCO can go without re-calibrating.)

    Regards,
    Dean