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CDC62005
Related Posts

  • Forum Post: Re: CDCE62002 Clock: Use sinewave as REFCLK?

    Fritz
    Sid, the CDCM7005 is an excellent performing clock jitter cleaner but it requires an external VCXO, which adds cost to the system. For systems that only need to generate a clean reference clock from a crystal or systems that need a jitter cleaner but can tolerate jitter in the order of 1ps rms the...
    on Aug 15, 2010

  • Forum Post: CDCE62005/CDCE62002 UIB

    Wen73818
    On CDCE62005 datasheet page 39, the input buffer parallel termination resisor is 50 ohm. But on CDCE62002 datasheet page 26, the resistor is 5K. What is the reason using 50 or 5K for seemingly same UIB?
    on Sep 19, 2011

  • Forum Post: Re: HSCL to CDCE62005/CDCE62002

    Wen73818
    So, the termination/bias scheme shoue be AC coupling, 10K_pu/10K_pd and 50 termination in this order, and close to CDCE62005 input. Can I use 100_pu/100_pd instead of 3 resistors?
    on Sep 19, 2011

  • Forum Post: Re: HSCL to CDCE62005/CDCE62002

    Wen73818
    OK, the 50 ohm termination is before the AC cap, (Not after). And after the ac caps, only a 10K_pu/10K_pd for bias, no termination. Please comfirm my understanding is correct. Thanks. But for CDCE62002, there is no termination at the receiver (CDCE62005 has), is that a concern?
    on Sep 19, 2011

  • Forum Post: Re: HSCL to CDCE62005/CDCE62002

    Wen73818
    Thanks for all of this. In my design, the HCSL driver go through long traces (from back plane) to other boards having CDCE62002 or CDCE62005. The HCSL driver vender suggest put the 50 ohm to GND close to the driver. Is it possible for you send me a drawing regarding the termination and bias scheme for...
    on Sep 19, 2011

  • Forum Post: Re: HSCL to CDCE62005/CDCE62002

    Wen73818
    Thank you very much.
    on Sep 20, 2011

  • Forum Post: CDCE62005 lock problem, recalibration unreliable

    Ali E.
    Hi, I am having problems reliably locking to the 100Mhz oscillator using CDCE62005. Our design sometimes starts up with the CDCE62005 locked, sometimes it is not locked. Initiating the manual calibration sometimes help get a lock, sometimes nothing happens. Here are the register settings: REGISTERS...
    on Jun 4, 2012

  • Forum Post: RE: CDCE62005 Output Synchronization uncertainty

    Stefano.
    Hello Timothy, Thank you for your answer, the component you've suggested seems very interesting. Regards, Stefano
    on Jun 28, 2012

  • Forum Post: CDCE62005 Output Synchronization uncertainty

    Stefano.
    Hello to all, for a new project i'm evaluating the CDCE62005 working in clock cleaner mode with programmable output skew. I've read the latest documentation for this component (also the technical notes for the newest CDCM6208 and some answers on this forum) and it seems there is an unavoidable...
    on Jun 24, 2012

  • Forum Post: RE: CDCE62005 no output0

    Canan Simsek1
    Hello Vladimir, Second idea : Time required for power supply to ramp with 20ms is short for device to realize your configuration. If you look at in datasheet page-67 in the topic of the start-up estimation. When you make delay 400ms, your device is already in the stabil position. So you can see output...
    on Feb 26, 2013

  • Forum Post: RE: HSCL to CDCE62005/CDCE62002

    Wen73818
    Hi, I generated a hex file using CDCE62005EVM. But when I programmed to chip through SPI for my real design, the PLL is never locked, the out freq not stable. The input is an very accurate 10MHx TCXO, placed nex to the chip input. My scope measurement is very stable 10 MHz. I am wondering if the hex...
    on Mar 28, 2013

  • Forum Post: HSCL to CDCE62005/CDCE62002

    Wen73818
    I am using HCSL drive (IDT 851010AYLFT) to drive CDCE62005. What is the proper termination for HCSL to CDCE62005 or the interface between the two chips? Thanks.
    on Sep 19, 2011

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