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SPI
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  • Forum Post: Re: CDCE62005

    Bagoj
    Hi Vijay! Got your message in the friend request. Unfortunately i couldn't find a satisfactory solution for my problem with the 72010. We've tried the AD9522 from ADI but -and this makes me look stupid- i had similar SPI problems with that. I'm sure that there is some power sequencing...
    on Jan 12, 2010

  • Forum Post: CDCE62005 LVCMOS TERMINATION PROBLEM

    Rolan Tang
    THE Application Report SCAA096 tell us when the ref input and output is LVCMOS, a 1K pull up resistor and 1K Pull down resistor are used, I wonder if they are really needed? I think series resistor is more improtant.
    on May 5, 2010

  • Forum Post: CDCE62005 SPI_MiSO open drain?

    Jan Schirok
    Hi, we're using the above TI clock manager CDCE62005 in a project (it also applies to CDCE72010). After reading the CDCE62002/CDCE62005 SPI related app note I found the MISO line being declared as "open-drain". This would imply, that the pin has to be pulled up externally via resistor...
    on Jan 26, 2011

  • Forum Post: Re: CDCE62002 SPI Read Operation

    mapefer3
    From bit0 to bit3 is the address of each register, bytes from 4 to 31 is the data of the register. For that reason there are two columns, one called SPI BIT and the other one RAM bit. When writing/reading any register, please send in the SPI protocol all 31 bits (including bits 0 to 3 that indicates...
    on Apr 18, 2011

  • Forum Post: CDCE62002 EVM Software settings for PLL lock

    Kerri Stone
    Hello: I am having issues setting register values in the CDCE62002 EVM Software. Specifically, I cannot setup the device to ensure PLL lock. I have a 10MHz input signal and wish to decrease the phase jitter on a 20MHz output signal. Attached is a screen shot with the current settings. What are...
    on Aug 29, 2011

  • Forum Post: cdce62005 can't lock

    guohua liu
    I used the “ CDCE62005 Controller GUI v1.4.4" generate a register value, then I configure them through SPI , the read back vaule of every register is right(same as the write data), but It can't lock anyway, is there any error or whether the chip is out of work? thanks (I don't...
    on Oct 9, 2011

  • Forum Post: RE: SPI rate of LMK04800

    Timothy T
    Hello, With the minimum times specified in the datasheet, 20 MHz is the fastest SPI rate. 73, Timothy
    on Sep 4, 2012

  • Forum Post: TRF371125: SPI interface 5V only?

    Max Koeppel
    Hi, I'm creating a broadband RX receiver using the TI TRF371125 IQ demodulator and the TI TRF3765 LO sythesizer (among others). I want to use them together on one 3.3V-SPI bus. Is this possible without risking damage/malfunction or do I definitely need a level shifter? From the datasheets I got...
    on May 21, 2013

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