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TI Home » TI E2E Community » Support Forums » Clocks & Timers » Clocks & Timers Forum » All Tags » pulling range
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pulling range
  • bq32000
  • CDCE72010
  • cdce72010 clock SPI
  • CDCE913
  • clock
  • clock & timers
  • clock generator
  • Crystal
  • I2C
  • I2C troubleshooting
  • jitter cleaner
  • LMK03806
  • LMK04
  • PLL
  • timer
  • VCXO
  • XTAL
Related Posts
  • Forum Post: Re: CDCE913 pullability - no hint that it's working....

    mapefer3 mapefer3
    In the datasheet of the XTAL you mentioned, the CL=18pF and the shunt capacitance is C0=7pF. +/-40ppm is the pulling range of the chosen XTAL calculated with the Pulling range tool included in the TI clock pro ( http://www.ti.com/litv/zip/scac119 ). You can find recommended XTALs to use the...
    on Jul 16, 2010
  • Forum Post: Re: CDCE913 pullability - no hint that it's working....

    mapefer3 mapefer3
    In the datasheet of the XTAL you mentioned, the CL=18pF and the shunt capacitance is C0=7pF. +/-40ppm is the pulling range of the chosen XTAL calculated with the Pulling range tool included in the TI clock pro ( http://www.ti.com/litv/zip/scac119 ). You can find recommended XTALs to use the...
    on Jul 16, 2010
  • Forum Post: Re: CDCE913 Output Problem

    mapefer3 mapefer3
    The CDCE913 has internal capacitors that you can program to match the crystal load specified by the XTAL datasheet. Therefore you might not need the external caps C80 and C81 that currently are in your schematic. That will fine tune the frequency of oscillation according to the pullability of the XTAL...
    on Nov 30, 2010
  • Forum Post: Re: BQ32000 clock source

    Yogesh Palkar Yogesh Palkar
    Hello Ryan Kehr sir, The crystal that is suggested is not available locally. So I have used a 32.768kHz crystal that is available locally. In general for these crystals we use a ceramic low value capacitor. As in for a microcontroller, we connect a 33pF capacitor. Now is capacitor connection necessary...
    on Mar 29, 2012
  • Forum Post: VCXO in LMX2541 PLL

    fernando henrique cardoso fernando henrique cardoso
    Hello guys... We are design high performance data acquisition system with 4 channels and we need to provide a ultra low jitter signal these 4 125 MSPS ADC´s that will do undersampling in a signal of 500 MHz. We need to use a PLL to lock the reference signal of 0.625 MHz and the output signal...
    on Apr 13, 2012
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