Clocks & Timers

Forum Post: CDCLVD1216 IBIS error

cafain — Fri, 24 May 2013 09:50:00 GMT

Hell, one Question.

I have a question about the IBIS-Model of CDCLVD1216.

I IBIS simulation using the Line Simv8.2.1 of Mentor.
Simulation at the start, an error message is displayed.
Why is this IBIS model. Please confirm.

Error message from the Mentor:
"Differetial pin 13 is paired with a GND pin in component CDCLVD1216 of file cdclvd1216.ibs"

Thank you.

Forum Post: RE: LMK04906 IBIS model

Alan Ocampo — Thu, 23 May 2013 21:00:00 GMT

I checked with our modeling team and found that we had a corrected version rev 1.1 made the day after this model went up, but the corrected version never got posted.

The corrected model should post overnight. Thanks for alerting us to the issue.

Best regards,
Alan

Forum Post: RE: LMK04906BISQ IBIS model downloaded today from TI has the wrong pinouts?

Alan Ocampo — Thu, 23 May 2013 20:57:00 GMT

I checked with our modeling team and found that we had a corrected version rev 1.1 made the day after this model went up, but the corrected version never got posted.

The revised model should post overnight. Thanks for alerting us to the issue.

Best regards,
Alan

Forum Post: Problem with Divide by N CD4059A

Simon Michaut — Thu, 23 May 2013 11:47:00 GMT

Hello all,

I'm working on a project which is using a Divide by N component, CD4059A. In fact, I have a problem with it.

I'm trying to configure it in order to have N=1000. So, I fixed input J1 (pin 3) and J13 (pin 10) at "1" logic. J2,J3,J4,J16, J15, J14, J13 are fixed to "0" logic (pin 4 to 9) as J5, J6, J7, J8, J9, J10, J11, J12 (pin 15 to 22)

L (Latch Enable, pin 2) is at "0" logic as kc (pin 11). Ka and kb (pin 13 and 14) are at "1" logic.

Vss (pin 12) is 0V (same value for inputs which are at "0" logic) and Vdd (pin 24) is 12V (same value for inputs which are at "1" logic).

My input signal is a square wave signal 12V peak to peak voltage, average voltage 6V 16.5 kHz but my output signal is 0V.

So, I would like to know if someone can identify my problem and give me a solution, please ?

Thank you in advance,

Simon Michaut,

Forum Post: RE: CDC Programming EVM installation problems

Henryk Bukowiec — Wed, 22 May 2013 15:52:00 GMT

I have a problem with my CDC Programming EVM. Drivers are installed correctly. The TiClock Pro can not find any boards. My operating system is Windows XP.

Best Regards

Forum Post: RE: parameters about LMK048**

jacky lu — Wed, 22 May 2013 14:36:00 GMT

Timothy:

In which document can I find this diagram?

Thank you!

Jacky

Forum Post: RE: LMK048XX/049XX clock for RF DAC

Noel Fung — Wed, 22 May 2013 03:47:00 GMT

Hi Jaime,

Yes, expect for Vcc2, Vcc3, Vcc10, Vcc11, Vcc12 and Vcc13 because LMK04906 has less clock output driver.

Forum Post: RE: Heat Slug on CDCM7005-SP

Timothy T — Wed, 22 May 2013 01:14:00 GMT

Lee,

[quote user="Liang Li1"]Is there any way that I can know the output resistance of CDCM7005-SP?[/quote]

It appears the eval board uses 22 ohms for LVCMOS, so I expect the output impedance is around 28 ohms.

73,

Timothy

Forum Post: TRF371125: SPI interface 5V only?

Max Koeppel — Tue, 21 May 2013 12:07:00 GMT

Hi,

I'm creating a broadband RX receiver using the TI TRF371125 IQ demodulator and the TI TRF3765 LO sythesizer (among others).

I want to use them together on one 3.3V-SPI bus. Is this possible without risking damage/malfunction or do I definitely need a level shifter? From the datasheets I got the impression that the digital interface of the TRF371125 is designed to operate at a 5V logic only?! Can VCCDIG be connected to 3V3 as well in oder to make the digital interface operate at that level?

Best Regards,

Max Koeppel

Forum Post: RE: Question of LMK0480XX

Timothy T — Mon, 20 May 2013 21:44:00 GMT

Hello,

I don't have an example at this time.

Within what time error must the clocks be synced? What frequency of clocks are on output?

73,

Timothy

Forum Post: RE: LMX2581 Synthesizer Jitter

Dean Banerjee — Mon, 20 May 2013 20:42:00 GMT

Joe,

Yes, it could do this. What I would do is a phase noise simulation and load in the noise into the OSCin pin. The simulation lets you disable a noise source so you can see the noise with our entered phase noise vs. the noise for a noiseless reference.

Regards,

Dean

Forum Post: Clock IC for AM3359 + TMS320VC5509 + ADS1274

Andre Luiz — Mon, 20 May 2013 20:39:00 GMT

I need a IC that can generate source clocks for these IC's on the same board: ARM AM3359 + TMS320VC5509 + ADS1274

Two of these outputs must have adjustable clocks output, like 27MHz or 37 MHz, selected by a control device (e.g. DSP or ARM).

Thanks!

Forum Post: RE: LMK00105 CLKin/CLKin* Input Clock Specifications

Noel Fung — Mon, 20 May 2013 09:54:00 GMT

Hi Hiroshi,

Yes, VIH and VIL = Vdd and GND respecitively. But the max voltage swing should be limited to 2Vpp. The latest datasheet (version F) has more details.

Forum Post: High resolution timing with MSP430F5438

Yannick Niane — Wed, 15 May 2013 15:58:00 GMT

Hi,

I'm using an MSP-EXP430F5438 Devkit + CC3000 module.I'm developping a wireless sensor node application. I need to find a way to have high resolution time-stamps for every data collected by the sensor node. Real time Clock is not enough since maximum resolution is second.

Any ideas on how i can have microseconds or even nanoseconds resolution time stamps?

Thanx

Yannick

Forum Post: RE: CDCE937 Questions

Julian — Wed, 15 May 2013 07:53:00 GMT

Hello Ushikubo-san.

Q1.

you can program the device directly after the supplies are stable. however i would recommend to wait 0.1us before starting the programming.

Q2.

After you set SPICON=1 the I2C interface is turned of, because the SDA and SCL became the control pins S1 and S2. You can not read back afterwards.

A: if you GND VDDOUT the I2C interface is still available through the control pins, even if SPICON=1. In this case the slave address is set to A0/A1=0. EEPROM write time is about 50us. if you wait 100us you can be sure that everything is written correctly.

B: Directly after EEPROM write is complete.

best regards,

Julian

Forum Post: consideration of clock system for ADS5474

jacky lu — Wed, 15 May 2013 04:42:00 GMT

Sir:

I need do a design with 4 ADS5474 to implement a interleaved ADCs, in which the sampling rate is 1.3G and each ADC works in 325M.

Now I have two clock schemes:

(1)One is used the dual PLL LMK04816, which can produce the clock with jitter of 100+ fs.

(2)The second is the recommendation of datasheet of ADS5474. In this method, I want use PLL to generate 325M clock and use BPF to filter the clock. Then, I use the XFMR to generate the clocks of 0, 90, 180, 270 degree phase ***. The below picture is the recommendation configuration from datasheet ADS5474.

I want to know, which method can get better clock? I need a sampling clock with minimum phase noise.

Is there any other better clock solution that is suitable for my application?

Thank you!

best wishes

Jacky

Forum Post: RE: LMK048** Detailed performance

jacky lu — Wed, 15 May 2013 03:55:00 GMT

Timothy:

Thanks for your reply and kindness! Because some reason in my lab, I can know consider this question again.

In page13 of datasheet LMK04816, the doc give two JITTER test meathod. One is "CLKout Closed Loop Jitter Specifications usinga Commercial Quality VCXO", the other is "CLKout Closed Loop Jitter Specifications using the Integrated Low Noise Crystal Oscillator Circuit".

(1)Dose the first means the LMK04816 works in dual PLL mode, and the second means the device works in single PLL mode?

(2)For the first test method, note16 indicate the VCXO used is CVHD-950-122.880, but the datasheet do not say which crystal it used. I mean the crystal that supply clock signal to CLKinX port.

(3)For the second test method, Crystal used is a Vectron VXB1-1150-20M480 and Skyworks varactor diode SMV-1249-074LF. Is there a schematic that show the connection?

(4) In your reply, you said the 100fs is the total jitter. What do you mean by the word "total jitter"? Is it the jitter including the jitter of reference clock, jitter of external VCXO and jitter of internal integrated VCO? Is it the total jitter of the output clock when LMK04816 works in dual PLL mode?

Thank you!

Best wishes

Jacky

Forum Post: CDCE62005 problem

Hitesh Shukla — Mon, 13 May 2013 17:42:00 GMT

Hi all,

I am using 2 CDCE62005 IC to get 10 outputs. These outputs I am using for clocking ADCs and DACs on my board. I am using under sampling to get 256/335 of 88 MHz.

These ADCs and DACs are used in phase and amplitude stabilization of a sinusoidal signal. When I program both initially it starts working, but after a shutdown the clock output shows strange noise that sometimes after reprogramming gets removed. As this card is to be delivered to a laboratory, this strange behavior is unexpected. The spectrum of the output clock sometime shows a varying spectrum of 9-11KHz. and the phase changes dramatically between 10 to degrees, but after reprogramming the phase variation remains of the order of 0.1 degrees.

I tried to change the power supply from initial to a better one presuming the backplane noise is entering the loop, but the situation remains same. When I program CDCEs initially output shows no noise, but after a shutdown of 1 hour, the noise starts coming again as soon as I program my FPGA.

I am not able to find the reason for this.

PLZ explain me what is wrong. I set the loop bandwidth using latest CDCE GUI it shows no warning and a very good phase margin of 55 degrees with a bandwidth 120KHz. with a spur of 41 db down. My charge pump setting is 1.25mA. Kindly tell me what is the problem if the clock output is jittery and in what way the synchronization takes place.

Kindly also tell me how can CDCE VCO be manually calibrated.

Thanks in advance.

Regards.

Forum Post: Can CDCE62005 been directly driven through Aux pin by TCXO?

xiang song — Mon, 13 May 2013 04:33:00 GMT

Can CDCE62005 been directly driven through Aux pin by TCXO?

In my last application, I use a clock buffer between the TCXO’s output pin (20MHz) and the CDCE62005’s PRI REF+/- pins.

Now, I want to simply the clock circuit, can directly link the TCXO’s clock output pin to Aux pin of cdce62005?

Thanks.

Forum Post: BQ32000 time drift issue.

Viral Chavda — Fri, 10 May 2013 08:57:00 GMT

Hi,

I have used BQ32000 rtc in my project and used 20ppm crystal. Now i have calibrated RTC with the crystal 20ppm but still i am facing rtc drift issue 3-5 sec/ 12 hours. Please suggest me how can i resolve BQ32000 rtc drift issue.