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CDCM7005
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  • Forum Post: Re: CDCE72010 / CDC7005 apllication questions

    Justo
    Hi John, Thanks for your email. The 50kHz input frequency is not a problem and both parts can work at that frequency. I recomend you not using AC coupling for the input, DC coupling is better for that input frequency. The CDCE72010 and the CDCM7005 have external VCXO. That means that if you...
    on May 26, 2010

  • Forum Post: CDCM7005, recommended caps for external loop filter

    mapefer3
    >>I have a CDCM7005 question: The EVM schematic uses Panasonic ECP film caps on the loop filter. Can I substitute the film caps for COG? What are the implications?
    on May 31, 2010

  • Forum Post: Re: CDCM7005/CDCM7005-SP with VCO

    Justo
    Hi Yuha, There are several aspects to consider when connecting a sine wave to the CDCM7005 one is the rising/falling time max of 3ns. Normally the sine wave has slow edges. Second point is the amplitude you mentioned 0dBm and 10dBm over. If 50 Ohms used then it is 0.224V and 0.707V respectively...
    on May 31, 2010

  • Forum Post: Re: CDCM7005/CDCM7005-SP with VCO

    Justo
    Hi Yuha, 260-320MHz sine wave it is okay then. If you can guarantee 0dBm min then you should be okay. The CDCM7005 will work even if the input is less than 500mV p-p but the AC specs can be a little bit worse. 2Vpp should be attenuated as you mentioned. Regarding the schematic it looks good...
    on Jun 1, 2010

  • Forum Post: Dose CDCM7005's Outputs have the same phase?

    Sheng Li53764
    If I set the same parameter, I mean the same divider M and N for different outputs, then dose all the outputs have the same phase? I need two clocks that not only have the frequency but also have the same phase, so I want to know whether this chip can satisfy my demand. Thanks for your reply.
    on Jul 21, 2010

  • Forum Post: Re: CDCE62002 Clock: Use sinewave as REFCLK?

    Fritz
    Sid, the CDCM7005 is an excellent performing clock jitter cleaner but it requires an external VCXO, which adds cost to the system. For systems that only need to generate a clean reference clock from a crystal or systems that need a jitter cleaner but can tolerate jitter in the order of 1ps rms the...
    on Aug 15, 2010

  • Forum Post: VCTCXO for CDCM7005

    Karppa65
    Hi, We have used Epson-Toyocom's TCO-2111T ( 768 MHz VCTCXO) as a clock source in our high-speed DAC design. The clock distribution circuit used is CDCM7005. Now we would like to find a backup / replacement for this VCTCXO, as delivery times tend to be very long. Any suggestions?
    on Aug 16, 2010

  • Forum Post: Re: VCTCXO for CDCM7005

    Fritz
    Hello Karppa, I have modified your post slightly to avoid discussing the performance of none-TI clock products. To check whether a clock source is applicable to the DAC you should investigate into the required phase noise spec. A publication in IEEE Transactions titled 'Direct Digital Synthesizer...
    on Aug 28, 2010

  • Forum Post: Re: CDCM7005 loop filter bandwidth

    Fritz
    Hello Stephen, "Jitter cleaning" by definition implies a low loop bandwidth. You would want to set the loop bandwidth so low, that you find great attenuation at any frequency of interest. For example, if you clock an ADC at 100MHz, and your DSP algorithm does data analysis over 256 samples...
    on Aug 9, 2011

  • Forum Post: Re: CDCM7005 loop filter bandwidth

    Fritz
    Hello Stephen, your summary of your first two paragraphs is accurate, nothing else to add. Concerning your question about the phase noise figure in the CDCM7005 data sheet, you need to consider the actual frequencies for each phase noise plot. The VCXO is running at 245.76MHz, while the outputs...
    on Aug 12, 2011

  • Forum Post: Re: how to achieve single-end clock input with CDCM7005 ?

    Fritz
    VBB can indeed provide the biasing for the unused, 2nd input. I think you should do the following: VCXO output --> AC coupling cap --> VCXO_INP VCXO_INP --> 10kΩ --> VCXO_INN VBB --> VCXO_INN VBB --> decoupling cap --> GND So basically the VBB signal biases...
    on Aug 12, 2011

  • Forum Post: CDCM7005QFN-EVM SPI control software

    George Biner (Arrow)
    We delivered a CDCM7005QFN-EVM to a customer today, but there was no GUI SPI software with it, and I cannot find online. C an you provide that? I think it only works on XP, but the customer does have an XP machine. Th anks very much. George Biner, Arrow LA FAE
    on Aug 18, 2011

  • Forum Post: CDCM7005 loop filter design

    George Biner (Arrow)
    hello, i am forwarding a customer inquiry for the CDCM7005: >>>> Could you please provide some assistance in choosing the right loop filter components for the Texas Instruments CDCM7005RGZ clock synthesizer? I cannot make out from the datasheet the right values and I am not gaining enough...
    on Dec 28, 2011

  • Forum Post: Re: How to generate fine frequency tunning (shift) in LMK04XXX or CDCEXXXX?

    Fritz
    I wonder if it would be best to first frequency synthesize with the LMX2541 and then jitter clean. The VCXO has sufficient tuning range, as you only seem to tune by +/- 1ppm total, while a VCXO is likely going to offer +/-100ppm tunability or even more. This implementation would get you the outputs for...
    on Feb 29, 2012

  • Forum Post: CDCM7005 can't set to "div by 1" output

    George Biner (Arrow)
    Hello: my customer has designed in the CDCM7005 into a system, and is having trouble seetting the output to /1. EAU is 50/yr, they will ultimately use the space grade version. regards, George Biner, Arrow FAE Los Angeles CDCM7005 application: 50 MHz reference input 1.6 GHz VCXO P divider...
    on Apr 2, 2012

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