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VCXO
  • CDC72010
  • CDCE72010
  • cdce72010 clock SPI
  • CDCE913
  • CDCE913 PLL VCTR
  • CDCE913's
  • CDCM7005
  • Crystal
  • jitter cleaner
  • KVCO
  • LMK03806
  • LMK04
  • loop filter
  • loop filter tool
  • PLL
  • pulling range
  • XTAL
Related Posts
  • Forum Post: Re: CDCE913 pullability - no hint that it's working....

    mapefer3 mapefer3
    In the datasheet of the XTAL you mentioned, the CL=18pF and the shunt capacitance is C0=7pF. +/-40ppm is the pulling range of the chosen XTAL calculated with the Pulling range tool included in the TI clock pro ( http://www.ti.com/litv/zip/scac119 ). You can find recommended XTALs to use the...
    on Jul 16, 2010
  • Forum Post: Re: CDCE913 pullability - no hint that it's working....

    mapefer3 mapefer3
    In the datasheet of the XTAL you mentioned, the CL=18pF and the shunt capacitance is C0=7pF. +/-40ppm is the pulling range of the chosen XTAL calculated with the Pulling range tool included in the TI clock pro ( http://www.ti.com/litv/zip/scac119 ). You can find recommended XTALs to use the...
    on Jul 16, 2010
  • Forum Post: Re: CDCE913 pullability - no hint that it's working....

    ivomarocco ivomarocco
    Dear Mr. Walthinsen, thank to your feedback we were able to spot a typo into the application note scaa085. C1 must be actually bigger than 20 femto Farad and not pico Farad. This will be corrected in pag.4. If you need to "pull" your frequency of a certain amount of ppm, you will...
    on Jul 19, 2010
  • Forum Post: VCTCXO for CDCM7005

    Karppa65 Karppa65
    Hi, We have used Epson-Toyocom's TCO-2111T ( 768 MHz VCTCXO) as a clock source in our high-speed DAC design. The clock distribution circuit used is CDCM7005. Now we would like to find a backup / replacement for this VCTCXO, as delivery times tend to be very long. Any suggestions?
    on Aug 16, 2010
  • Forum Post: Re: CDCE913 Jitter Problem

    mapefer3 mapefer3
    It might be a signal integrity issue. How is the jitter being measured? Are you measuring the jitter at the output of the CDCE913 when is driving the video decoder circuit with and without Vctr? How does the clock output looks like? Would it be possible to get some screenshots of the CDCE913 output...
    on Oct 22, 2010
  • Forum Post: Re: CDCE913 Output Problem

    mapefer3 mapefer3
    The CDCE913 has internal capacitors that you can program to match the crystal load specified by the XTAL datasheet. Therefore you might not need the external caps C80 and C81 that currently are in your schematic. That will fine tune the frequency of oscillation according to the pullability of the XTAL...
    on Nov 30, 2010
  • Forum Post: Re: CDCE72010 unlock issue debug

    Fritz Fritz
    Muralidhar, you need to make sure that the entire PLL setting including the loop filter is actually stable. You can not simply power up on the EEPROM default settings unless you have your loopfilter designed such that it cooperates with your device configuration. Please download the loop fiter tool...
    on Feb 23, 2011
  • Forum Post: Re: Provide a VCXO 1Ghz to CDCM7005

    Shawn Hintermeyer Shawn Hintermeyer
    Jose, I would certainly recommend going up to 1ghz as well with your vcxo. The crystal that you use should be the correct frequency to get the right timing. here is a list http://www.oscilent.com/catalog/Category/vcxo.htm of some other 1ghz VCXO that might help you.
    on May 13, 2011
  • Forum Post: Can CDCE913's Vctr pin to be fed with sine wave input ( e.g. 0~5khz ) for VCXO feature ?

    Stanley Tseng Stanley Tseng
    As titled, one of my customer is testing our CDCE913 EVK and they plan to use CDCE913's VCXO function by using Vctr pin. They want to utilize the linearity area of Vctr ( i.e. the voltage between 0.7V to 1.2V per the graph shown on Figure 4 of Application Report -- "SCAA085". i.e...
    on Jan 17, 2012
  • Forum Post: VCXO in LMX2541 PLL

    fernando henrique cardoso fernando henrique cardoso
    Hello guys... We are design high performance data acquisition system with 4 channels and we need to provide a ultra low jitter signal these 4 125 MSPS ADC´s that will do undersampling in a signal of 500 MHz. We need to use a PLL to lock the reference signal of 0.625 MHz and the output signal...
    on Apr 13, 2012
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