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Question: The CDCM61004 Datasheet states on page 20: "for proper operation, the LVCMOS reference should be available and fairly stable by the time the power supply voltages or the RSTN pin voltage on CDC... reaches 2.27V."
--> What does the word stable mean?
Answer: Upon releasing reset the device goes into a self-calibration routine for the crystal input stage. In order to make this stage accept a clock reference input signal instead, the clock signal must be valid and within range at the time when the device goes into the calibration routine. If the Reference Clock signal is not available during the time of calibration, the self-calibration will fail and cause the device to malfunction until the next reset cycle. Hence the LVCMOS input clock signal needs to be running with full signal amplitude and with a clock frequency within a few hundred ppm of the target frequency.”
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