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1. Is the hardware trigger active in the DDC264 evaluation board?
What is the amplitude and shape of the input trigger signal that can be issued into J4 after “Fast Data” has been pressed?
The hardware trigger mode is not implemented in this evaluation board. Hence disabling or enabling the Hardware Trigger will not have any effect during the data capture.
2. DDC264EVM install guide for 64bit versions of Windows 7, 8, 10
There’s a complete guide on installing the DDC264EVM evaluation software and troubleshooting drivers for 64bit versions of Windows 7 through 10 here: https://e2e.ti.com/support/applications/medical/f/30/t/285994
3. What is the cause for an offset in the output code between side-A and side-B on the same input channel?
This is due to the internal mismatch of the different components in the circuit. As long as the mismatch is within the Offset Mismatch Specifications, it is normal.
4. Is there any EOL or longevity information on the DDC devices?
There is no intention of obsoleting any of the DDC parts. TI obsolescence policy is stated here:
5. Why is the DVALID signal sometimes inverted to the DDC264 Datasheet specifications?
The behavior is normal if DXMIT and DCLK are not being used to read out the data. DVALID is low when the data is ready to be read out. If the data does not get read out, DVALID needs to go high again briefly before dropping low to show that data is once again ready. The figures in the datasheet assume that data is getting read out soon after DVALID goes low which causes DVALID to go high again when DXMIT is pulled low and DCLK is toggled to read out data.
6. Can the DDC be used to measure leakage current in a circuit in the order of 10nA?
The input of the DDC is basically a virtual GND, so, if the leakage path can be connected on some way to that input, then sure, it can be measured... The other limitation is that the current has to be INTO the device (see for instance page 8 of the DDC232 datasheet). To measure currents coming out of the device, see (link to the other FAQ).
7. Can the AGND be shorted with the DGND?
Please refer to layout recommendations on the device's datasheet.
8. Can you daisy chain one DDC114 and a DDC118 device because this can help reduce space cost and a number of SPI?
You should be able to chain together the DDC118 and DDC114 but the issue then would be difficulty in the data readout and similar. For applications like this we usually tie DCLK together for all devices in the chain and you would need to be sure that you pay close attention that you would need to clock the DDC118 more than the DDC114 since the 8 would be giving you twice the channels.
The two devices are based off the same silicon and have the same specs so that should help if you do decide to use one of each device.
9. Is it possible to power the DDC264EVM entirely from USB?
The board was not intended to be powered from USB alone. USB can only reliably provide up to 500mA which is not enough to power the whole board.
10. I am going to use the same power supply for both FPGA and the DDC2256A with necessary ferrite bead in between. Let's say, I use the same LDO output 1V8 for both FPGA I/O and DDC2256A DVDD_1V8. The LDO can afford the load current. The FPGA can only be ready after the DDC2256A is ready due to the FPGA power-on sequence requirement. Do you think there are any problems for this design regarding device function, noise?
There are 4 supplies to the DDC2256A device: 2.5V AVDD, -2.5V AVEE, 1.8V AVDD_18 and 1.8V DVDD. If all the analog power supplies (2.5V, -2.5V and 1.8V) either ramp up at the same time or before 1.8V DVDD, then there shouldn’t be any problem with that particular device level power on sequencing.
The requirement from DDC2256 is that RESETz and EN should be held low during power up and RESETz should become high only after all the supplies are stabilized. Since the RESETz pin has an internal 50K PU resistor to DVDD, during power-up, the RESETz signal will be low and after the power supplies ramp up, the RESETZ becomes high through the PU resistor.The EN pin has an internal 50K PD resistor to AGND, during power-up, the EN will be low and after the power supplies ramp up, the EN will remain low until the FPGA is ready to set EN high and then program the configuration registers. When EN = 0, the outputs are tristated.
11. Is there any EVM for the DDC232 as the closest thing that seems available is the DDC264EVM?
Unfortunately we don't offer an EVM for the DDC232. There are EVMs/PDK kits available for the following devices:
We do recommend the DDC264EVM as it is closest to the DDC232.
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