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Part Number: ADS1299
I'm testing acquisition of EEG data with ADS. I have included the chip on a custom PCB with the necessary power supply (from battery) and signal conditioning for the input signals. A raspberry pi (RPi) is used to acquire samples from the amplifier through SPI.
To test data acquisition, I have two GPIO pins on the RPi generate delayed 10Hz and 7Hz square waves (between GND and 3.3V), which are then attenuated by voltage divider network by 100 before feeding into IN1P and IN2P of the amplifier. GND is fed into SRB1 of ADS, and the ADS operate in referential montage with respect to SRB1. The VSSA and VDDA for ADS are -2.5 and +2.5V. This works as expected and I acquire the different 10Hz and 7Hz waveforms (described by box 1 in the Figure 1 below).
I then want to test the right-leg drive by the bias amplifier. My test setup is indicated in box 2 in the Figure 1: the attenuated square waves are buffered and summed with Vbias before entering ADS. I configured the bias amplifier to take the average of the measured signals. This resulted in something similar to that in Figure 2 (Vbias calculated as the average of the input signals):
On the scope the output (original+bias in the figure) has ripples due to the Rf-Cf feedback of the bias amplifier. While the results are exactly what I expected, I am not sure if my test setup models RLD correctly -- in the original+Vbias plot, during the time period where the 10Hz and 7Hz overlap, the frequency information is lost distorted.
The purpose of RLD is to enhance common-mode rejection...an alternative I could think of is to add a small common mode Vcm to V1 and V2 (box 3 in Figure 1). But it would still not be able to preserve the 10Hz and 7Hz information in the resulting signals.
I have read the SBAA188 application report on right-leg drive, in its test setup in Figure 7, it applies the same signal to both input channels (one through RC-network, the other no RC-network). But this does not address the distortion of the measured signals by the bias signal. Am I understanding this correctly? What is the correct way to model the effects of RLD?
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I'm a little confused by what the Matlab plots are referring to - please try to clarify this for me:
Also, remember that you are driving square waves into the device, which are comprised of many higher frequency components than the fundamental 7 Hz or 10 Hz. The BIAS amplifier closed-loop bandwidth is currently set to ~133 Hz, so the common-mode cancellation signal at the BIAS amplifier output will not contain those higher frequency components and you will not be able to reject them. Can you substitute V1 and V2 with 300 mVpp amplitude sine waves from a function generator?
A couple comments on the schematic drawing:
Precision ΔΣ ADCs
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In reply to Ryan Andrews:
Thanks for the quick reply. Sorry for the inaccurate plots, the Matlab plots were to demonstrate the shape of the waveforms. The clarifications:
1. "Original" is showing the output of Channel 1 and Channel 2 without VBIAS summed. The configuration is as you described, gain of the PGA is 24. The square wave was generated in the 0-3.3V, then attenuated to 0 - ~40mV by the voltage divider before entering the PGA.
2. "VBIAS" - this is calculated, to describe the output of the BIAS amplifier. I measured the shape and frequency on the actual BIASOUT pin with the scope and it agrees with this calculation.
3. "Original+VBIAS" - this is the expected output of Channel 1 and Channel 2 with the circuit (2) configuration. My expectation is exactly as you describe, i.e. "the BIAS output will contain both signals in the circuit you have drawn, so I believe 7 Hz will show up on Channel 1 and 10 Hz will show up on Channel 2"
So here lies my trouble in understanding RLD -- say both Channel 1 and Channel 2 has frequency components [f1, f2, ...fn], all within the closed-loop bandwidth, with each frequency component containing different amount of power for different channels. If I take their average and apply inverse of that to cancel the common mode, that would add Channel 2's frequencies onto Channel 1, and vice versa. This then distorts the actual frequency contents in both channels. Is my understanding correct, or am I not testing this correctly?
You are right that V2 should be connected between the 100K and 1.2K resistor, just like V1...silly mistake on my part. And you are right, I omitted the PGA between the INxP and 220K BIAS sense resistor...I was taking the gain for granted.
In reply to Allen Yin9:
Alex SmithApplications Engineer | Precision Delta-Sigma Converters
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In reply to Alexander Smith:
I have read this post and other papers on RLD and understand and agree with the theory and what you said. I am having problem testing and applying this, specifically in the situation I outlined where feeding back the common-mode signals result in introducing channel 1's frequencies into channel 2, and vice versa. I'm wondering if you could comment on any problems with my test setup, and on how I can tell if RLD is indeed working in a given setup.
I still have not resolved the issue...I replaced the square waves with sine waves, and the same problem persists -- the bias signal formed from averaging individual channels contains frequency components of all the input channels and therefore each recorded channel gets injected with the other channels' frequency components. It is not clear to me how impedance mismatch in each channel can solve this. Although if both channels are contaminated with common mode noise, say 60Hz power line, the 60Hz noise will be subtracted from the input channels.
So far, my conclusion about the RLD is that it indeed removes common mode noise, but mixes the differential mode...I'm thinking one possible solution is to set the bandwidth of the bias amplifier to below the EEG signals of interest (say below 1Hz). But this approach would not be able to filter out high frequency common mode noise (which may not matter too much since EEG bandwidth is limited to below 50Hz). Any suggestions?
So like this:
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