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ADS1158: Trace specifications

Part Number: ADS1158

G'day,

Following on from the linked question, I'm in the process of laying out my two ADS1158 ADCs. I'm finding it particularly difficult to manage space on the board, and was hoping for some guidance on the input analogue signal traces. I'm currently using 10 mil traces with 20 mil spacing; is this enough, not enough, too much, etc.? Reducing the 20 mil spacing would certainly alleviate the space issue I'm having, but I don't want to jeopardise signal integrity in doing so.

Thanks!

  • Hi jars121,

    Interesting question! When I think of "signal integrity" (SI) issues I normally associate these concerns with digital communication but certainly you can apply SI concepts to analog signals as well.


    Regarding how to size the trace width for the ADS1158 analog inputs, I think this would depend on the type of signals you are working with...

    For DC and low-frequency signals, the parasitic inductance and capacitance of the traces won't have much effect on the signal. For low frequency signals, the trace resistance is probably more important to consider. Therefore, depending on the amount of current you expect to have flowing through the trace you can size the trace accordingly. Since you are likely buffering your input signals with a high input impedance amplifier(s), then your signal currents should be very small and trace widths for the analog inputs don't need to be exceptionally large.

    For higher-frequency AC signals or signals with fast edges, the trace's parasitic inductance and capacitance starts to affect the signal. In this case it becomes very important to make sure that all traces are routed above a ground plane without any gaps or cutouts below the trace. Trace lengths should also be kept as short as possible. If you are concerned about AC coupling between traces, then I would recommend keeping trace lengths as short as possible, routing all analog traces above a ground plane layer (to have much more capacitive coupling to ground than to nearby traces), and if possible adding a ground fill (or guard trace) in between traces (especially for clocks and other signals with fast edges). See www.edn.com/.../PCB-signal-coupling-can-be-a-problem.

    In summary...
    Since you are most likely working with low-frequency signals on the analog inputs, I would probably make my trace widths (prior to the buffer) about 8 mils and then a little wider after the buffer (since transients and slightly higher currents are more likely on the buffer's output). I would then make the gap between the traces as wide as I could afford for the PCB space allowed - if this allows for a ground plane fill between traces then that is great, but if not then focus on keeping the trace lengths short.

    Best regards,
    Chris


    Christopher Hall
    Applications Engineer | Precision Delta-Sigma Converters

    Check out our helpful resources:
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  • In reply to Christopher Hall:

    Hi Chris,

    Thanks for your valued input, as always I greatly appreciate it! Everything you've written makes sense. All components and traces are on the top layer, which has an unbroken GND plane directly beneath it, so from that perspective I'm pretty comfortable. Whether I can fit a guard trace as well is another question entirely!

    Below is what I'm currently working with. I have a 16x2 2.54mm pitch through hole connector, which provides all 32 analogue signals for the circuit. The outer white line is just a 2mm virtual boundary I use to comply with the PCB manufacturers requirements, with the smaller white rectangle my virtual analogue section. I.e. no digital signals are allowed in, and no analogue signals are allowed out. I can resize this rectangle as required.

    As you can see, I have the two ADS1158s straddling the rectangle at the top of the board, with the op amp components directly underneath. Each analogue input is voltage divided, then passed through a BAV199LT1G protection diode array. I've got 16 of the 32 signals (the left ADC) traced in the below image, but think the traces are going to be far too long. I've played with about a dozen configurations, but trace length is always an issue. Ideally I could have the ADS1158s directly to the left of the signals, so the signals can trace straight from the diodes to their corresponding inputs. With this approach however, the digital side of the ADCs would be on the very edge of the board, which I'm guessing is far from optimal? See the second image below as an example; the yellow line is the board edge. If it's ok to have the digital section between the board edge and the analogue section, then this approach seems logical I think?

    Image 1: Current/attempted layout, noting obvious trace length issues.

    Image 2: Potential layout with more direct traces, but with the digital section between the board edge and the analogue section.

    Any input/guidance would be greatly appreciated!

    Thanks!

  • In reply to jars121:

    Hi jars121,

    I think the issue your facing is not necessarily the best orientation for placing all of the devices, but perhaps the required PCB area taken up by the BAV199L diodes. Do you have the option to move half of these diodes, and maybe the opamps as well, to the bottom side of the board?

    I might also try looking for diodes and op-amps with smaller package options to reduce the trace lengths. Which op-amp do you currently use for buffering the ADS1158's MUX ouput?

    I'm not an ESD expert, but take a look into something like the TVS0500 for use as an input protection device. It has slightly higher leakage current than the BAV199L and it clamps at a higher voltage (so you would need a series resistor after it for current limiting), but it comes in a very small package and appears to be able to take quite a beating.

    For the digital routing, I would try to avoid routing the digital traces below analog traces, below the ADCs, or too close to the ADC clocks (are U6 and U76 oscillators, or something else?). As long as the digital traces are partitioned (are routed through a separate PCB region) I don't see an issue with having them on the side or top of the board. Obviously you want to keep the digital traces short too, so you might need to find a compromise that prevents excessively long traces on either the analog or digital side.

    Best regards,
    Chris


    Christopher Hall
    Applications Engineer | Precision Delta-Sigma Converters

    Check out our helpful resources:
    TI Precision Data Converters | TI Precision Labs - ADCs | Analog Engineer's Calculator | Data Converters Learning Center | Selection Guide

  • In reply to Christopher Hall:

    Hi Chris,

    Thanks for your prompt response. I can certainly move the diodes and opamps to the bottom side of the board if need be. I'm using a 4 layer stack (signal, GND, PWR, signal); do I need to use stitching capacitors if I put these components on the bottom side?

    I'm currently using OPA365 opamps, which were one of the recommended options you gave in an earlier post of mine. As for the diodes, I've gone with the BAVs as they provide dual rail clamping in the single package (i.e. will clamp negative inputs to VSS and excessive voltages to VDD). The size and format of the TVS0500 looks ideal, but from a brief look it seems to only protect against over voltage, not so much for reverse polarity.

    Thanks for confirming the digital trace placement. I'll make the digital traces as short as possible, without compromising any of the 'analogue only' sections. Since my reply yesterday, I had a go populating the layout with the ADCs on the right (per the second image in my previous post). This is what I came up with:

    I think this is heading in the right direction. If the opamp and potentially resistor divider and diode circuits are placed on the bottom, I should be able to shorten the traces considerably. Not currently shown in the layout is a pair of 16-channel MCP23017 IO expanders. Each analogue signal is connected to a channel on the MCP23017 via a 1kOhm resistor, to provide a 5V reference for unpowered signals (e.g. a 2-wire thermistor) if needed; for powered sensors with an external voltage reference, the corresponding channel on the MCP23017 can be made a high impedance input, effectively removing the 5V, 1kOhm pullup. I can arrange how the MCP23017s are laid out once the above considerations have been addressed.

    Yes, U6 and U76 are the oscillators for each of the ADCs. I meant to ask in my initial post as to the best location for them. I had originally planned on having a single oscillator for both ADCs, but given the separation between the two ADCs, I figured I'd have to use individual oscillators. Is that the case? I don't need the ADC readings to be synchronised between the two ADCs, so if it's simpler to implement 2 oscillators then I'm happy with that. In terms of location, are they fine where they are, as long as I maintain a wide berth between them and the SPI signals?

    Final question, I've added thermal vias to the exposed pad, per the reference TI document in the ADS1158 datasheet. As you can see in the above image, the pad is connected to AVSS, with the vias connected to GND. Given that I'm trying to maintain a virtual separation between the digital and analogue sides of the ADCs, do I need to worry about the exposed pad connecting to GND on both sides of the virtual separation? I don't believe so, but figured I'd ask.

    Thanks!

  • In reply to jars121:

    Hi jars121,

    Nice, that is a more compacted layout!

     

    jars121
    I'm using a 4 layer stack (signal, GND, PWR, signal); do I need to use stitching capacitors if I put these components on the bottom side?

    If you have ground plane fills on the top and bottom layers, then you should certainly add ground vias scattered around the board to connect the multiple ground planes/fills.

    A stitching capacitor is typically used to connect between different ground pours, in the case where you split the analog and digital grounds, for example. However, I don't think you have multiple ground nets or split ground planes, correct?

     

    Regarding the OPA365 opamps, are you using the SOIC package?

    The OPA365 also comes in a smaller SOT23 package, but I might also suggest using the OPA2365 (the dual version of the OPA365). The OPA2365 only comes in a SOIC package, but you would only need one OPA2365 per ADS1158, which should save you space.

    The TVS0500 is unidirectional, but I believe it protects against reverse voltages as well since the diode is forward biased and it conducts at -0.5V:

     

    jars121
    Yes, U6 and U76 are the oscillators for each of the ADCs. I meant to ask in my initial post as to the best location for them. I had originally planned on having a single oscillator for both ADCs, but given the separation between the two ADCs, I figured I'd have to use individual oscillators. Is that the case? I don't need the ADC readings to be synchronised between the two ADCs, so if it's simpler to implement 2 oscillators then I'm happy with that. In terms of location, are they fine where they are, as long as I maintain a wide berth between them and the SPI signals?

    I think you could go either way with shared or independent oscillators. Independent oscillators makes the layout a bit cleaner and the clock trace(s) shorter; however, a shared oscillator saves you some space and might allow you to keep the clock a little further away from the ADCs.

    If you can use both sides of the PCB for the protection diodes and squeeze the ADCs closer together, I might try to share a single clock.

     

    jars121
    Final question, I've added thermal vias to the exposed pad, per the reference TI document in the ADS1158 datasheet. As you can see in the above image, the pad is connected to AVSS, with the vias connected to GND. Given that I'm trying to maintain a virtual separation between the digital and analogue sides of the ADCs, do I need to worry about the exposed pad connecting to GND on both sides of the virtual separation? I don't believe so, but figured I'd ask.

    AVSS and GND are both at the same potential correct (i.e. AVSS isn't -2.5V), correct?

    By "virtual separation" I assume this isn't a physical ground plane cutout, so there is shouldn't be any concern in having this thermal pad exist on both sides of the virtual grounds. By partitioning analog and digital signals into different regions, return currents flowing on the ground plane will naturally remain separated. AND, should there be any cross overs, the reduced impedance (from having a solid ground plane instead of separated grounds connected at a single point) means that there is less common-impedance coupling between signals.

     

    Best regards,
    Chris


    Christopher Hall
    Applications Engineer | Precision Delta-Sigma Converters

    Check out our helpful resources:
    TI Precision Data Converters | TI Precision Labs - ADCs | Analog Engineer's Calculator | Data Converters Learning Center | Selection Guide

  • In reply to Christopher Hall:

    Christopher Hall

    Hi jars121,

    Nice, that is a more compacted layout!

    Getting there!

    Christopher Hall

    If you have ground plane fills on the top and bottom layers, then you should certainly add ground vias scattered around the board to connect the multiple ground planes/fills.

    A stitching capacitor is typically used to connect between different ground pours, in the case where you split the analog and digital grounds, for example. However, I don't think you have multiple ground nets or split ground planes, correct?

    Correct, I have a single, solid GND plane on layer 2. So I will place components on the back of the board, and add a GND fill around the components/traces on this layer, then connect this fill with the solid GND plane with scattered vias.

    Christopher Hall

    Regarding the OPA365 opamps, are you using the SOIC package?

    The OPA365 also comes in a smaller SOT23 package, but I might also suggest using the OPA2365 (the dual version of the OPA365). The OPA2365 only comes in a SOIC package, but you would only need one OPA2365 per ADS1158, which should save you space.

    I am using the SOIC package; from memory I didn't think I'd be constrained for space. As for the OPA2365, that looks like a great option; Mouser seems to be short on stock, but I'll do some more research. With the opamps on the back side I might be ok with the dual OPA365s, but I'd always choose a single IC over multiple if possible.

    Christopher Hall

    The TVS0500 is unidirectional, but I believe it protects against reverse voltages as well since the diode is forward biased and it conducts at -0.5V:

     

    Thanks for that; if I can't make the current design with the BAVs work I'll look to give these a go.

    Christopher Hall

    I think you could go either way with shared or independent oscillators. Independent oscillators makes the layout a bit cleaner and the clock trace(s) shorter; however, a shared oscillator saves you some space and might allow you to keep the clock a little further away from the ADCs.

    If you can use both sides of the PCB for the protection diodes and squeeze the ADCs closer together, I might try to share a single clock.

    I'll see how I go with this one as well. The ADCs are a lot closer now than they were before, so I might get away with a shared clock after all.

    Christopher Hall

    AVSS and GND are both at the same potential correct (i.e. AVSS isn't -2.5V), correct?

    By "virtual separation" I assume this isn't a physical ground plane cutout, so there is shouldn't be any concern in having this thermal pad exist on both sides of the virtual grounds. By partitioning analog and digital signals into different regions, return currents flowing on the ground plane will naturally remain separated. AND, should there be any cross overs, the reduced impedance (from having a solid ground plane instead of separated grounds connected at a single point) means that there is less common-impedance coupling between signals.

    Correct, AVSS is at GND potential, I'm measuring between 0 and 5V, not -2.5 and 2.5V.

    Correct, as mentioned above I have a solid GND plane, and am only 'separating' analogue and digital GND using placement.

    With that said, I've put the OPA365s on the reverse side of the board, and have maintained the top-side placement of the voltage divider and current limiting resistors and protection diodes. Shown below is one of the ADCs, with the traces now much more direct between the 2.54mm input header and the ADC itself. NOTE: as I mentioned in my previous post, I'm using an IO expander to provide programmable (i.e. on/off) pullup resistors to my 5V reference. With the layout shown, the IO expander will be placed on the reverse side of the board (not shown); the vias on each of the analogue signal traces will connect the signal trace to the corresponding 1kOhm pullup resistor (which is then connected to the corresponding channel on the IO expander).

    Picture 1: Current layout with opamps moved to reverse side of board. NOTE: PWR and GND vias not yet placed.

    Will having the signal trace pass through a via like that cause any issues? I'm aware that at higher frequencies it could introduce some antennae-like behaviour, and that the via has different impedance characteristics to that of a standard trace, but I don't think I'll be able to connect the traces to the pullup/IO expander circuit without the use of vias.

    I've used MCP23017 IO expanders in the past, and had planned on using them here as well. I think I'll opt for 4 8-channel IO expanders rather than 2 16-channel ICs, as the traces from each bank of 8 vias would be much simpler and shorter. Final question: can you recommend a TI 8-channel IO expander which is 5V-tolerant, and can source >10mA per channel?

    Thanks as always!

  • In reply to jars121:

    Hi jars121,

    I don't think the vias will be an issue with your analog signals.

    Regarding the I/O expander, take a look at this list: http://www.ti.com/interface/i2c/general-purpose-io-gpio/products.html#p1752=8;24&p106max=5;6&p886=VCC&p2192=Configuration Registers;Reset Pin&p1498=Catalog&o4=ACTIVE

    I looked through several of these device datasheets and found that the PCA9554A is capable of driving a bit more current that some of the other I/O expanders, (upwards of 45 mA) per channel.

    Best regards,
    Chris


    Christopher Hall
    Applications Engineer | Precision Delta-Sigma Converters

    Check out our helpful resources:
    TI Precision Data Converters | TI Precision Labs - ADCs | Analog Engineer's Calculator | Data Converters Learning Center | Selection Guide