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ADC12DJ3200: Output sample bit order JMODE3

Part Number: ADC12DJ3200

Hello, 

I read in the datasheet that samples are transmitted MSB first, and LSB last. However, in the JMODE data format tables, it is not clear to me which bit of each octet is first and last. This is what I understand:

When I receive the first byte of this frame, for lane 0, I will get
A0(11) ... A0(4) in the first byte
A0(3) ... A0(0) A8(11) ... A8(8) in the second byte.
A8(7) ... A8(0) in the third byte.
...

I am considering the left bit of my descriptions to be the MSB of the byte, and the right bit the LSB of the byte.

Is this the correct interpretation of the JMODE 3 table?

  • Hi Cameron,

    I have notified the device owner. He will get back to you shortly.

    Jalen
  • In reply to Jalen Tate89:

    Hi Cameron

    Your interpretation is correct regarding how the ADC data is framed and transmitted through the link.

    The way the FPGA IP output the data is in blocks of 32 bits. The data ordering may be somewhat different once it is in that domain.

    Please see this earlier E2E thread where I decode the bit ordering in the Xilinx format provided by the customer. The 32b values are displayed as 4 octets in hex format. The earliest octets are at the right and the later octets move to the left. So decoding can be pretty confusing at first.

    I hope this is helpful.

    Best regards,

    Jim B

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