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DAC38J84: DAC38J84EVM + TSW14J10EVM + ZC706 issue

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Replies: 22

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Part Number: DAC38J84

Dear all

i am developing a FPGA based arbitrary waveform generator, have the system components  (DAC38J84EVM + TSW14J10EVM + ZC706).

i have made the connection and tried the use of HSDC pro +DAC3XJ8X GUI and configured and tested the generation of tone successfully.

Now my question is, i would like to use Vivado system design software suit for arbitrary waveform generation... can you provide example project based on my system ?

if its not available can you please help me developing the vivado based project ?

any help in this regard is highly appreciated 

thanks

  • In reply to Kang Hsia:

    HSDC pro screenshots.pptxHi Kang.

    i have attached the ppt which includes screen shot of HSDC Pro setup. 

    Once again i am clarifying what i want to do,

    task: Generation of customized waveform (range of 80 MHz) at maximum possible sampling rate of DAC 38J84.

    so basically i need to know the setup for maximum sampling rate output setting.

  • In reply to Ravikant Pandey:

    DAC38J84_841_1228.8M.pptxDAC38J84_841_983.04M.pptxRavikant,

    Attached are two setup files to follow to get what you want. Since the -2 FPGA device on the ZC706 has serdes that are only rated to 10.3125Gbps, the 1228.8Msps case may not always work. It did work on my setup when I tried it though. The second file I have attached slows things down to 983.04Msps to stay within the spec of the device.

    Regards,

    Jim

  • In reply to jim s:

    Thanks Kang and Jim

    Now i am able to generate customized waveform .

    i have another issue i am generating .CSV file of 65536 samples in matlab. The array of samples looks like fine in matlab.

    but when i am loading the file to HSDC Pro,  and doing all the setup as usual i am still not getting output at DACs.

    could you please tell that .CSV file uploading in detail...in my case i am using MATLAB.

    note. I am able to generate test files at DAC output.

    thanks in advance

  • In reply to Ravikant Pandey:

    Ravikant,

    the loading of the .csv file instructions are in section 3.7.2 of the HSDC PRO user's guide
    www.ti.com/.../slwu087d.pdf

    There are example files that you can following in the default directory.

    -Kang
  • In reply to Kang Hsia:

    Dear Kang

    thanks for your support.

    i am able to generate customized patterns using my set up now, i have another issue..please suggest me some solution.

    due 16 bit DAC the number of samples are limited to 65536 so as length of waveform.

    i want to use this set up to generate different custom waveform together which are sequenced with each other.

    is their any method to generate such sequenced customized waveform like general arbitrary waveform generators..?

    any help will be appreciated..

    thanks in advance

    Ravikant

  • In reply to Ravikant Pandey:

    Basically i want to do.....Unique Real-time Sequencing that Links Multiple Waveform Files Creating Wave forms of longer length.
  • In reply to Ravikant Pandey:

    Ravikant,

    The 16-bit DAC resolution is the resolution of the DAC output swing and the granularity of the output swing (i.e. how fine we can represent the Y axis). It has nothing to do with the length of the pattern (i.e. X axis or time resolution). The length of the pattern is limited by your FPGA design. You will need to include DDR memory in your FPGA design to increase the length of the pattern being loaded onto the pattern generator. Using the on-chip memory of the FPGA sounds like are not sufficient for your design.

    -Kang

  • In reply to Kang Hsia:

    Hi kang
    thanks for help and suggestions
    Now please help to extend the memory as i am using ZC706 evaluation kit which has 1 GB DDR3 memory, please tell how can i add this memory to my FPGA design. do i need to change the Firmware..? or some setting in DAC38J84 GUI..?
    help is appreciated, its very urgent for me...
  • In reply to Ravikant Pandey:

    Hello Ravikant,

    Sorry, TI in general cannot help with additional development of FPGA firmware design for you. I would advise that you contact Xilinx directly for support.

    -Kang

  • In reply to Kang Hsia:

    hello Kang..

    thanks for suggestions

    i am seeking for help and suggestions from TI because i am following the set up settings of 

    (DAC38J84EVM + TSW14J10EVM + ZC706) as given in manual of TSW14J10EVM and HSDC pro user manual.

    Now i am in middle of something and just need to use the memory of ZC706 board in pattern generation so that i can upload pattern file of longer length in HSDC Pro.

    i request you again for any optional suggestion.

    thanks

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