Part Number: ADS54J60
Dear TI,please clarify the following inconsistencies from datashet of ADS54J60 (revision January 2017):1) Table 14 suggest for LMFS = 4211 operation the JESD mode to be set to 0x4. Table 17 suggest 0x2. Which is correct / what is the difference?2) JESD digital page (0x6900) register 0x7 read back after initial resets shows 0x9. This is contradictory to Table 56 which implies 0x4 to be default value. Which bit should be set to select subclass 1? Bit 0 or bit 3? What about the MSB?3) General registers 3 and 4 are marked R/W in table 20/21. Yet I never succeeded in reading them (0xc003 / 0xc004).Thank you in advance- Jiri
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In reply to Jim Brinkhurst84999:
Hi Jim,thank you for the answers!. Just to note: default readback after power-up on the chips that I have, for the question 2) is not 0x8 but is 0x9, hence the origin of the question. So then what about the LSB, can it be zeroed, or must be written with 1?Best regards
In reply to Jiri Kral83:
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