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Part Number: DAC60501
I seek for clarification.
In one of the videos (Precision DACs: DC Specifications), LSB is calculated as equal to Vref/2^n. One reference (The Fundamentals of Mixed Signal Testing) I've come across, LSB is equal to FSRdut/2^n - 1; FSR is the measured full scale output range of the device.
These two equations don't appear to agree with each other. If anyone has the insights on how to resolve this, I would appreciate it so much.
This is a fun question! One thing to note is that the full-scale range of the DAC is not really VREF. Consider an 4-bit R-2R ladder and a 5V reference. We can say that the VLSB = 5V/(2^4) = 5/16 = 0.3125V.
With all switches connected to the ground node (DAC code = b0000), the output is 0V
With just one switch connected to the reference (DAC code = b0001) the output is 1LSB, 0.3125V
With all switches connected to the reference (DAC code = b1111) the output is 4.6875V. But isn't that the fullscale range? Should that be Vref?
Basically, as 4-bit DAC cannot have code 16 applied to it, because then that would require another bit. So the fullscale range of the DUT (FSRdut) can be expressed as FSRdut = Vref(2^16 - 1)/(2^16).
Here is the tina-ti simulation:R2-R.TSC
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In reply to Paul_Frost:
In reply to Abe Hortillano:
We do not use the Vzero-scale value. If we are trying to calculate the real VLSB (the VLSB that includes the real reference voltage, not the ideal voltage), we measure the output at two points, generally not the endpoints.
DACs have error specific error at the endpoints due to the output range getting clipped by the power supply. Consider if the DAC is only powered by one supply, 5V. The ideal range is 0-5V, but realistically the output amplifier cannot drive the output to 5V and 0V.
We calculate VLSB, offset error, and gain error by measuring two points. On a 12bit DAC that might be code 32 and code 4064 (32 LSB from the endpoints). We then calculate VLSBreal = (Vout(4064)-Vout(32)/(4064-32).
The zero-scale error is different than the offset error. If you draw a line between the two points just measured, the point where it crosses the y-axis is the offset error. Because of the non-linearity of the DAC output near the supply rails, the zero-scale error is different than the offset error. The zero-scale error equal to the voltage at code 0, because ideally the zeroscale would be 0V.
Does that clarify things a bit?
Also, make sure to check out our learning center: ti.com/pdlc.
Thank you Paul. Your input on the methodology of calculating the real VLSB is a good one. You're great!
The lecture videos from the TI Learning Center are of sure help to my understanding. However, my further research on this matter led me to the Maxim Integrated ADC and DAC Glossary (see attached photo). They've got different answer.
Isn't there an industry standard definition of these terms? Thank you Paul.
This is a really great question! My colleagues over at maxim are correct too, but they did not explain all cases. Let's start by talking about why we care about offset error (OSE). I think a good way to think about it is to also consider gain error (GE). For this scenario we will say that GE is in units of % and OSE is in units of V.
If you know your GE and your OSE for a DAC, then you could correct the error with the following calibration equation:
So for that reason, we care what OSE and GE are for a DAC.
There are DACs where the offset error (OSE) and zero-scale error are the same. Consider this TINA-TI simulation where I model a DAC with a potentiometer, where the wiper position is the input code and the output is 0V to 1V. In this case, we will say this DAC has no gain error, but I added a -100mV offset error with a voltage source.
By sweeping the POT input we see the simulated DAC's output transfer function. The voltage across the POT is the ideal DAC output, while the voltage that includes the offset is the real output.
In this case you see that the ZSE is equal to the OSE and both are -100mV. So we can use either to correct the error of the DAC in the equation I listed earlier. So in this case the guys at maxim are correct.
Most DACs have a output buffer, which is just an op amp. Most amplifiers have a rail-to-rail input and/or rail to rail output limitation, or at the very least they cannot output a voltage that is lower than their lowest supply. If we add an amplifier to the TINA-TI simulation, you can see how this rail to rail limit changes the output transfer function.
So now the OSE error and the ZSE error are different! But which one would you want to use in the calibration equation? Only the OSE value would correct the majority of the curve. The limitation at the supply is unavoidable and cannot be corrected, so the ZSE really just lets the user now the range where the DAC has linear behavior.
I guess those maxim jokers never thought of that!
Hope this helps! Here is the simulation: OSEvsZSE.TSC
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