This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Part Number: ADS1198
We are using TI's ADS1198 8 channels at 250SPS (4ms) rate with 5V AVDD and 4V as internal reference. ADS1198 is connected to a snapdragon via SPI and using android sensor framework to read the data on every DRDY signals. we are facing two issues in our system with ADS1198:
1. sampling rate (sampling period) varies drastically from 1ms to 6ms event though it is set at 250SPS (4ms)
2. signal attenuation happens on the actual signal and it varies as we change the sampling rate, with higher the rate lower attenuation
can you suggest the potential root causes that may lead to these issues and possible test scenarios to exactly pin-point source of the issue?
Alex SmithApplications Engineer | Precision Delta-Sigma Converters
Check out our helpful resources: Common Questions for TI's ADS129x Family of Bio-Potential ADCs
TI Precision Data Converters | TI Precision Labs - ADCs | Analog Engineer's Calculator | Data Converters Learning Center | Selection Guide
We are glad that we were able to resolve this issue, and will now proceed to close this thread.
If you have further questions related to this thread, you may click "Ask a related question" below. The newly created question will be automatically linked to this question.
In reply to Alexander Smith:
Thank you very much for your reply.
1. sampling rate variation looks like coming from varied handling of DRDY by the android sensor framework and we are now investigating it. we will come back if any further questions on this.
2. our input signal is a real muscle EMG signals captured by the sensors attached to the arm skin, so it is 15 to 25Hz. so if the sinc filter has attenuation roll-off, how can we improve it? the datasheet shows that it can be changed by changing DR bits in config1 resister but DR bits actually changes the sampling rate which we want to keep at 250Hz fixed.
thank you in advance for your effort.
In reply to Bhagvan Ramolia:
Hi Alexander this idea looks interesting. let us try that out. however, we suspect that with 500Hz sampling rate, interrupt will be generated at every 2ms and even if we do reading at every alternate interrupt, our system still need to do some house keeping at every 2ms and which may break the timings of our sensor framework. but let's see the outcome. thank you again for your good suggestion.
we tried changing sampling frequency to 500Hz and then reading the samples at 250Hz. it definitely improves the frequency response. now the -3dB frequency shifts from originally 65Hz to 130Hz that's that good improvement. however, we have seen some strange issue with output signal quality. i input the pure sinusoidal wave and varied the frequency from 1Hz to 500Hz. at input frequencies which are integral divisor of 500Hz, e.g. 250Hz, 125Hz, etc the shape of the signal really goes bad, looks like it brings aliasing effect or introduces some harmonics of the input or sampling frequency to the oroginal signal. any solution?
Thank you for your reply.
Attached are the data files 125Hz.xlsx250Hz.xlsxf digital output signals for 125Hz and 250Hz input sinusoidal signals. Yes, we are using the internal clock of the ADS1198. No external clock.
we are reading the data via SPI on every alternate DRDY, with actual sampling rate of 500Hz and data reading output at 250Hz. after directly reading the data, we convert using floating point and transfer to a file. we do not see a problem at 10Hz signal. 10Hz data file: 10Hz.xlsx
also we do not see a problem if used 250Hz ADC sampling rate and data read also 250Hz.
in a particular file, all data is only for output. input for that output is always fixed at 2Vpp+1.5Vdc sinusoidal signal with frequency equal to that file name. in each file, the output data-set is captured for ~10 seconds recording and different graphs in the same file are nothing but a plot of different time length data-set from the same file starting from the first reading.
SCLK reads are not overlapping with DRDY in any of the data-sets as we have had conformed that through logic-analzer on the SPI bus. that is also confirmed by not having the similar issue if we have input frequency e.g. 1Hz, 5Hz, 10Hz, 25Hz, etc...but only seen on 125Hz and 250Hz only. by the way we are reading off the DRDY pulses, not timing. we don't see the varied handling of the DRDY by android sensor framework anymore and that is confirmed that it is resolved.
250Hz graph at left bottom is actually a onsecond data plotted and it actually does not represent 250Hz at all. all the data is completely messed up by the filter of the ADC. we do not see the proble at 62.5Hz and 31.25Hz. our frequency of interest is ranging from 10Hz to 200Hz.
I too suspect some kind of aliasing effect by the ADC and sinc filter.
All content and materials on this site are provided "as is". TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with regard to these materials, including but not limited to all implied warranties and conditions of merchantability, fitness for a particular purpose, title and non-infringement of any third party intellectual property right. No license, either express or implied, by estoppel or otherwise, is granted by TI. Use of the information on this site may require a license from a third party, or a license from TI.
TI is a global semiconductor design and manufacturing company. Innovate with 100,000+ analog ICs andembedded processors, along with software, tools and the industry’s largest sales/support staff.