• Resolved

TSW14J56EVM: Provided Verilog firmware does not compile

Prodigy 150 points

Replies: 9

Views: 141

Part Number: TSW14J56EVM

I need to modify  the TSW14J56 firmware to allow multiple captures before offloading data. I downloaded the firmware provided, but with no modifications it doesn't compile successfully in Quartus II 14.1, which I believe is the environment it was developed in. Compilation yields the following error:

Error (125091): Tcl error: ERROR: Option "-qip" for "UNFORCE_MERGE_PLL_OUTPUT_COUNTER" assignment is illegal. Specify a legal option or remove the option.

while executing
"set_instance_assignment -name UNFORCE_MERGE_PLL_OUTPUT_COUNTER ON -to "*jesd_avgz_pll_0002*|altera_pll:altera_pll_i*|*""
(file "gzPLL/jesd_avgz_pll/jesd_avgz_pll_0002.qip" line 2)
Info (125063): set_global_assignment -name QIP_FILE gzPLL/jesd_avgz_pll/jesd_avgz_pll_0002.qip -qip gzPLL/jesd_avgz_pll.qip -library jesd_avgz_pll

The file mentioned contains only two lines:

set_instance_assignment -name PLL_COMPENSATION_MODE NORMAL -to "*jesd_avgz_pll_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name UNFORCE_MERGE_PLL_OUTPUT_COUNTER ON -to "*jesd_avgz_pll_0002*|altera_pll:altera_pll_i*|*"

Why doesn't the provided firmware compile? Am I making some mistake? I have only worked with VHDL and Xilinx boards before, so I am new to both Verilog and Quartus.