Part Number: ADS54J64EVM
The mode 6 (IQ 125MSPS) is not supported in HSDC pro software. We would like to try it in our carrier board with FMC connector.
Is still possible set the mode 6 with ADS58J64 EVM GUI (JP3 set to USB mode)?
We would like to bypass CPLD with JP3 set to FMC mode.
What is funcionality of CPLD in this configuration?
What is purpose of signals FMC_D5, FMC_D6 and FMC_DIR_CONTROL?
Thanks and Regards
In reply to jim s:
I have fixed problems with JESD stability and NCO.
Now I'm facing problem with full-scale behaviour of the ADc. ADS54J64 should have full-scale range 1.1V so with 50ohm input it should have circa 4.8 dBm.
I observe full-scale swing on the IQ data when the kit ADS54J64EVM is fed with circa 7-8dBm. I have checked voltage on differental inputs that swing is circa 1.5V. Also FOVR (set to -0.5 dBFS) functionality indicates overrange when swing exceeds circa 1.45V. The power from signal generator was also checked that it is 8 dBm
Why I observe full-scale circa 1.5 V and not 1.1V? Do I overlook something?
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In reply to Daniel Stindl:
Do you have the pass band of the decimation filter set correctly? In the CHX page, try setting address 0x78 to 0x03.
I'm basically interested in VHF band 90–110 MHz. This is reason why I select LPF config and first Nyquist zone. NCO in mode 6 is set for circa 90 MHz.
The ADS58J64EVM is evaluated in TSW14J56EVM and in our Xilinx board where I can see separated IQ outputs from JESD. I can still confirm that full scale is around 8 dBm and not for 4.8 dBm.
I have attached screens from High speed data converter for circa 4 dBm. Also I can't interpret complex FFT. It seems there is unbalance in IQ data.
The problem with full-scale in mode 6 can be fixed with using mixer compensation (don't know why it is disabled by default) and with digital gain (sampler level) for expense of NSD degratation.
The problem with IQ imbalance in mode 6 still remains. IQ lanes are swapped and one of the channel is one sample delayed to the other (see attachment I vs Q). I have reproduced it in our evaluation board.
Can you please help me? I still believe there is something wrong with register configuration sequence for mode 6. The log from ADS58J64 EVM GUI doesn't make sense according to datasheet. The are several writes into undocummented registers etc.
I vs Q
I am just returning from vacation and behind on many posts. I will try to look into this issue ASAP but this may take a few days.
I tried to do some reverse engineering with ADc configuration but I was unable to get it work correctly. The problem with IQ imbalance in mode 6 remains unsolved. :(
just update for someone facing similar problem.
We have temporary fixed the problem with IQ unbalance by doing correction in our FPGA. Basically we swapped lanes in correct order and shifted one sample in Q channel so I->Q is 90°. With this fix the performance (NSD, SNR, ENOB at 125MSPS) is usable for our application.
The last problem we have with NCOs reset so the phase are aligned. We tried feed SYSREF input with bursts (before SYSREF powerdown, reg 0x6A:0x02) without a success. Is there something what should we be aware of?
We have tried to feed ADc with 500MHz and use mode 1 for achieving 125MSPS output (cause of lower clock frequency and lower decimation the performance should be same) but we couldn't establish the JESD link (in TSW14J56EVM with user guide or in our FPGA board). SPI sequence is same except set the mode 1, reference clock for FPGA JESD RX 125MHz, JESD RX setting same...
I have a question about the ADS58J64. Is it basically ADS54J64 with burst mode instead averaging funcionality? Is there chance it could work better with our desired configuration?
Mode 6 will work. Just set address 0xAD and 0xAE to 0x06.
With JP3 set to FMC mode, the following signals from the FMC connector will be used by the CPLD to control the ADC and LMK SPI:
FMC_SCLK, FMC_SDIO, FMC_SDO, FMC_SEN_ADC, and FMC_SEN_LMK.
If you were to use the ADC or LMK in 3-wire SPI mode, the CPLD would use the FMC_DIR_CONTROL to determine if the data line is used for writes or reads. FMC_D5 and FMC_D6 are spare signals from the FMC.
The CPLD source code is attached. If required, you can modify as needed by the controller driving the FMC pins.
3652.ADS54J64EVM CPLD Code.zip
Today I had problem with establishing jesd communication what worked yesterday. The SYNC signal is not asserted because K28.5 (0xBC) is seen only on lanes B C and D. I don't know what happened...
https://tutuapp.uno/ , https://9apps.ooo/ , https://showbox.kim/
In reply to snow jhon:
Did you issue a hard reset to the ADC after the clock was present?
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