Part Number: DAC38RF82
we are testing DAC38RF82 now, we face some problems and need your help;
1.FDac(DACCLK)=7200M,External Diff Clk;
2.Single DAC(DAC A)
3. 1 IQ pairs
4. 8 serdes lanes
6.output IF analog signal=1.7GHz
9.FPGA GTH refclk=150MHz
Secondly,Our DAC38RF82 register configuration :
1. We read register 0x64 to 0x6D ,the result as below(DACLANE0_Error ~ DACLANE7_Error)
DACLANE0_Error ~ DACLANE7_Error=0x2000
2.The JESD204B Link chain between DAC and FPGA is always attemping to establish
In reply to jim s:
I want to add something
If I set JESD_SYNC_REQ register 0x151=0x00DF,Bypass link configuration error;The JESD204B Link chain between DAC and FPGA is also established,we also can get an valid output data;
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In reply to Wong:
In this case, what is the setting of 0x14F bit 5? If this is set to 1, then the link errors are ignored by register 0x151 bit 5. In either case, you can bypass or ignore link configuration errors using either one of the two registers.
Either "bit5=1" of 0x14F or ''bit 5=0" of 0x151,The JESD204B Link chain between DAC and FPGA is always established;DAC has data output;
Jim,I'm going to block this out temporarily;Thank you for your help during these days;
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