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ADS8866: Quiet time in 3-Wire mode.

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Replies: 2

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Part Number: ADS8866

Hello,

What are the requirements on tquiet?

In the datasheet timing diagram (Figure 1) the end of tquiet is at the rising edge of CONVST but when is the start defined?

and what should be inactive during this time?

Many thanks!

/Takeshi

  • Hello Takeshi,

    Welcome to the TI E2E Community.

    I need to check with the team, but t-quiet should be the time from the last SCLK edge (16 falling edge in above diagram) to the rising edge of CONVST.  In other words, there should be no digital activity on any of the digital control lines for the 20nS preceding the rising edge of CONVST.  This is necessary to get the full 16b  noise performance out of the device.

    I should have a confirmation by end of business tomorrow.

    Thanks!

    Regards,
    Keith Nicholas
    Precision ADC Applications

  • In reply to Keith Nicholas:

    Hi Takeshi,

    The above suggestion is the safest approach; avoid any digital activity on the digital lines for 20nS prior to the rising edge of CONVST in 3-Wire mode.  However, the key source of noise coupling is due to the SDO line driving external capacitance.  (The digital and analog supplies share a common ground in this device.)  The last transition of the SDO line will occur on the 15th falling edge of SCLK plus a delay of td-CK-DO=13.4nS.  This would be the precise point where you need to observe the beginning of the quiet period.

    If you can ensure no digital activity for 20nS before CONVST rising edge, this is the best approach.  However, if you cannot meet this requirement but the above definition, you can still get good noise performance with the last falling edge of SCLK occurring during the t-quiet period.

    Regards,
    Keith

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