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ADS127L01: wrong settle time after reset

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Replies: 6

Views: 179

Part Number: ADS127L01

Hi all,

From database, td(NDR) is 84 when using wideband filter, means that three should be 84 FSYNC pulses between the deassertion of RESET and the first valid DOUT,

but actually, the first valid DOUT appears at the 85th FSYNC rasing edge.

And for the low latency filter, actual latency is not the same as datasheet too.

There is an example for osr=00, filter=11: low-latency mode with osr=32, from datasheet, the latency should be 5, but actually, it is 7.

  • Hello,

    Our primary support engineer for this family of devices will get back with you on Monday.  Until then, any more zoomed in images and possibly oscilloscope captures of the waveforms will help in the analysis.

    Collin Wells
    Precision ADC Applications

  • waveform captured for osr=2'b00, filter=2'b10, frame-sync master mode

    restoring from power down mode (just ignore the glitch on reset_n pin)

    after 1.15ms ~= 18728 tCLK, the device exits power down mode

    zoomed version

    you can see that there are 7 FSYNC pulses before the first valid DOUT

    but datasheet says it should be 5.

  • In reply to tiamo:


    Thank you for providing the detailed logic waveforms.  Please give me until Friday to discuss with the design team.

    Also, if you have access to an oscilloscope, please measure the /RESET, FSYNC, and CLK pins, similar to Figure 88.  There may be a small timing discrepancy that is not captured with the logic analyzer.  Specifically, It would be helpful if you can measure t-su(RSM).

    Thank you,

    Keith Nicholas
    Precision ADC Applications

  • In reply to Keith Nicholas:


    I was able to reproduce the power-up delay and measured 7 FSYNC periods for osr=2'b00, filter=2'b10, frame-sync master mode.  For a mode change, I measured 6 FSYNC period delays.  In both cases, the FSYNC period was constant, so the initial delay appears to be rounded up by 1 FSYNC pulse.

    In the case of the power-up delay, I think the additional FSYNC delay period was due to the supply voltages ramping at a slow rate, but I need to investigate this more.

    I still need to discuss this issue further with the team.  However, the ADC does behave consistently.  I would suggest allowing for the additional time in your system when there is a mode, power-up, reset, or other change in the ADC configuration.

    The digital filter settling times are fixed based on the design of the filter and these will be consistent during normal operation of the device.

    Please give me a few more days to follow-up.


  • In reply to Keith Nicholas:


    I have taken some additional measurements, both for a mode change, as well as a full reset, and have duplicated the measurements that you took.  I was hoping to confirm this behavior with the designer, but I have not been able to sync up with them.

    Since I was able to replicate these measurements on the ADS127L01 evaluation board, this strongly suggests that this is the typical behavior when using frame-sync master mode.  Please use 85 FSYNC periods for the wideband filters, and 7 FSYNC for the low latency filter options.



  • In reply to Keith Nicholas:


    There is no problem if the delay is constant, just wait a litter longer.