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Hello,

My application is Folw-Cytometry, and I will use multi-channel data acquisition board design.

I am very interested at this chip. I have two questions about the application of this chip:

1. About the input clock frequency of LCLKP/N, normally LCLKP/N(31/32 pin) is 7 times of CLKP/N(72/73 pin).

But when the decimation 4 is enable, what is the input clock frequency of LCLKP/N? 7/4 times of of CLKP/N?

And there is the same question about  ACLKP/N

Pin LCLKP, LCLKN -- Differential LVDS bit clock (7X)

Pin ACLKP, ACLKN-- Differential LVDS frame clock (1X)

1. About the AD driver. We plan to use differential amplifier to drive ADS5294. Is it possible to place the differential amplifier in another board, the differential signals are sent to ADS5294 through HDMI wire.

Is this a requirement to place the differential driver close to ADS5294?

• Hi,

Regarding the LVDS bit clock and the frame clock, you are correct. The LVDS bit clock and the frame clock scales down based on the decimation factor.
The LVDS bit clock frequency (LCLK) is dependent on the sample rate and the type of wire interface (1-wire or 2-wire). And the sample rate is factor of the input clock rate and the decimation factor.

In 1-wire mode, ACLK = Fs/M (Hz), where M is the decimation factor and Fs is the sampling frequency. LCLK = 7 * Fs/M (Hz). The “output data rate” is 14 *Fs/M (bps) or 7 * Fs/M (Hz). Please note the units.
In 2-wire mode, ACLK = 0.5 * Fs/M (Hz), where M is the decimation factor and Fs is the sampling frequency. LCLK = 3.5 * Fs/M (Hz). The “output data rate” is 7 *Fs/M (bps) or 3.5 * Fs/M (Hz).

Normally it is recommended to keep ADC driver on same board as ADC, otherwise line between ADC and driver is not well characterized and can cause reflections in presence of ADC sampling, which can result in performance degradation.

Regards

Praveen

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