• State TI Thinks Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 48 subscribers
  • Views 1125 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADC12DJ3200EVM: ADC12DJ3200EVM query

Star Xu
Genius 9645 points
Part Number: ADC12DJ3200EVM
Other Parts Discussed in Thread: TSW14J57EVM, ADC12DJ3200

Hi

My customer test the ADC12DJ3200EVM, they measured the noise power density by terminating the input with 50ohm. Then got results like -80dBFs/4.5MHz i.e -147.1dBFs/Hz. But as per Data Sheet -151.8dBFs/Hz should come. Can what could be the reason for this 4dB Delta?

Waiting for your reply

Thanks

Star

  • 0
    TI__Genius 9645 points

    Attached the error screen shot.

    What is the minimum sampling freq I can use in ADC GUI. Why asking this question means when I went to 800 MSPs and  JMODE0 with DDC gain boost on and cal trigger running on .I am getting error while capturing the data. Similarly can you tell me minimum sampling frequency with highest decimation factor.

    Thanks

    Star

  • 0 in reply to Star Xu
    TI__Intellectual 2750 points
    Star,
    I have sent this question to an engineer
    Regards,
    Brian
  • 0 in reply to Brian2001
    TI__Mastermind 43910 points

    Hello Star

    It is possible to operate with Decimate by 16 and 800 MHz clock rate, using JMODE15.

    Lane rate limitations of the TSW14J57EVM capture firmware limit the minimum clock rate to higher minimum frequencies and lower maximum frequencies for specific JMODEs. The current supported lane rate range is from approximately 3.2 Gbit/sec to 12.8 Gbit/sec. The lane rate for a given JMODE and CLK frequency can be calculated using the R parameter in Table 18 in the ADC12DJ3200 datasheet.

    Best regards,

    Jim B