Dear Support team,
Our customers are considering using LMP92066 for 3.5G macrocell applications.
They are studying the safety of the equipment and have questions about the FETDRV output voltage of LMP92066.
They use the LMP92066 in GaN mode (VSSB= -5V).
Questions about the voltage of the FETDRV output driving the GaN power FET.
Question 1
In the GaN mode, no voltage is applied to VDD and VIO, and -5V is applied only to VSSB.
DRVEN pin is GND level.
Under this condition, always output -5V as output from FETDRV?
Question 2
A recommended voltage is also applied to VDD and VIO from the state where -5V is applied only to VSSB.
DRVEN pin is GND level.
In this case, will the FETDRV output rise to near 0V(GND level)?
Question 3
The VDD voltage or VIO voltage is turned off from the state where the normal voltage is applied to VDD, VIO, and VSSB.
In this case, will the FETDRV output rise to near 0V(GND level)?
Best Regards,
Hiroaki Masumoto