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LMP92066: Questions about FETDRV output voltage when using GaN mode

Part Number: LMP92066

Dear Support team,

Our customers are considering using LMP92066 for 3.5G macrocell applications.
They are studying the safety of the equipment and have questions about the FETDRV output voltage of LMP92066.
They use the LMP92066 in GaN mode (VSSB= -5V).
Questions about the voltage of the FETDRV output driving the GaN power FET.

Question 1
In the GaN mode, no voltage is applied to VDD and VIO, and -5V is applied only to VSSB.
DRVEN pin is GND level.
Under this condition, always output -5V as output from FETDRV?

Question 2
A recommended voltage is also applied to VDD and VIO from the state where -5V is applied only to VSSB.
DRVEN pin is GND level.
In this case, will the FETDRV output rise to near 0V(GND level)?

Question 3
The VDD voltage or VIO voltage is turned off from the state where the normal voltage is applied to VDD, VIO, and VSSB.
In this case, will the FETDRV output rise to near 0V(GND level)?

Best Regards,
Hiroaki Masumoto

  • Hiroaki-san,

    I will look into these questions. With the holiday season in the US responses may be delayed, but I hope to get answers to you be next week.

    Thanks!
    Paul
  • Paul-san,

    I am looking forward to hearing from you.

    Best Regards,
    Hiroaki

  • Masumoto-san,

    I apologize for the delayed reply. Paul has been out of office this week at a trade show, therefore many of his support threads have encountered a delay. In the meanwhile myself and some of the other Applications Engineers will attempt to get you a reply tomorrow.

    Otherwise, Paul is back in office on Monday to continue work on this thread.
  • Howdy Masumoto-san,

    Just to add to my colleagues inputs, I believe there is a similar question at the following link:

    e2e.ti.com/.../2397277

    Page 7 of the datasheet indicates Vih and Vil levels for the DRVEN pins, therefore for correct operation VIO should be established before other supplies when driving these pins.  Once VIO is established, you can then drive these pins low if you wish to safely power the device, and drive the DAC output to VSSB.

    It is important to note that there is a small power-up transient on the DAC output when VDD is ramped, and this is shown in Figure 50 of the datasheet.  Therefore the recommended power sequencing is VIO, VDD and lastly the source to the power amplifier, which should ramp after the VDD power-up transient passes.

    Best Regards,

    Matt

  • Hi Hiroaki-san,

    Sorry for the delay in collecting this data.  Please see the image captures for the difference conditions.

    Q1: VDD=VIO=~0V, VSSB = -5V, DRVEN = GND

    In this case FETDRV follows the VSSB supply to -5V.

    Q2: VDD=VIO=5V, VSSB = -5V, DRVEN = GND.  

    Case 1: Supplies power up at the same time:

    In this case the FETDRV follows the VSSB supply as well.

    Case 2: VSSB is already established, VIO and VDD are supplied after VSSB:

    FETDRV stays at -5V.

    Q3: VSSB and VDD, VIO are established, VDD and VIO are disabled

    In this case the FETDRV stays at VSSB as well.

    And as a supplemental case:

    Q4: VIO and VDD stay on, VSSB is disabled:

    FETDRV follows VSSB and goes to 0V.

    Please let me know if this answers you inquiry.

    Thanks,

    Paul

  • Paul-san,

    Thank you for your kindly reply.
    This measurement result is my inquiry.

    I will explain it to my customer.

    Best Regards,
    Hiroaki Masumoto