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TSW14J56EVM: trigger capability and TSW14xx synchronization

Part Number: TSW14J56EVM

Hello

I would like to use the following ADC, DAC & capture EVMs for our experimental setup

TSW14J56 -> ADS54J20EVM (dual channel, 12bit, 1GSPS ADC)

TSW1406 -> DAC5682ZEVM (dual channel, 16bit, 1GSPS DAC)

I wanted to confirm that our requirements can be met with this

1) I need the ADC and DAC sampling to be synchronized. What is the best way to do this and what kind of timing precision can we expect ex, within 100ps? Do we need the TSW1400 for this or will the TSW1406 work?

2) We want to play out a signal pattern from the DAC that is say 50us long and simultaneously capture ADC samples

3) We want to repeat this multiple times with say 10us gap ie, play out the signal every 60us

4) We would like to generate a trigger signal every time this process starts ie, every 60us?

5) We would like this process to repeat till the TSW14J56 memory fills up at which point the DAC and trigger signals stop as well.

6) Do you have suggestions on how to minimize the data transfer time to a PC. What kind of throughput can we expect from the "TSW14J56  -> PC" over USB3.0. A rough guidance would help.

7) An alternative for us might be to use "TSW14J56 -> DAC3XJ8XEVM (dual channel, 16bit, 1.6GSPS DAC)" instead of the above TSW1406/DAC5682ZEVM combination if it makes things easier/more precise

Thank you.

  • Hello Majid,

    I do not know much about the DAC setup for triggering with the DAC+TSW, but the ADC+TSW evaluation is set up for single trigger captures.  Meaning that if you want to record multiple captures before offloading data you will need to create your own firmware for the FPGA.  

    The data transfer time from FPGA to PC (using HSDC Pro) is not very efficient with the current HSDC Pro build.  We have improvements planning to release later this year, but they will only improve trigger to display.  We only support automation through the HSDC Pro tool.  

    Automation examples are available in the installation directory

    C:\Program Files (x86)\Texas Instruments\High Speed Data Converter Pro\HSDCPro Automation DLL\Manual and Examples

    Regards,

    Brian

  • Hi Brian

    Thanks for this information. I found some docs on the TI website and have some related questions:

    1) This one suggests with a USB3.0 interface to the TSW14J56 "user can capture 1GBytes in ≈ 20 seconds". Please see page 4, 3rd para from top.
    www.ti.com/.../slwu087d.pdf
    Is my interpretation correct that I can download 1GByte of data samples from DDR memory to the PC in ~20sec?

    2) You mention "We only support automation through the HSDC Pro tool.". Is there any significant additional overhead (in terms of time delay) when I call the HSDC tool commands via the automation API?

    3) We can probably make a single initial trigger work as well by synchronizing the 2 TSW capture boards. The same document above "section 3.1.3.3 Trigger Operation" suggests use of the "TRIG_IN" and "TRG_OUT" SMAs on the TSW capture boards to synchronize start of the DAC processing and ADC sampling. I am still curious though what the expected (typical) delay is from the "TRIG_IN" signal to the start of data converter operation? Where can I find this.

    4) In addition for (3) above, we will need to provide a common reference clock to all boards (ADC and DAC). What is the best way to do this.

    5) I assume that we can specify the single capture length to be long enough to fill up the full DDR memory ie, ~2Gsamples? So if we are operating a dual channel ADC each channel will have 1G sample memory?

    Thanks.
  • Hello Majid,
    1) Yes, depending on the firmware utilized you should be able to transfer at that rate
    2) Yes, there is some additional latency (msecs) with the automation API. It is not fully deterministic so I cannot offer any performance metrics.
    3) I am going to send your question over to an engineer that might be able to offer help on the synchronization question
    4) same as 3
    5) Yes, you can run a single capture to fill the DDR and then transfer. The number of capture samples available is based on the converter and configuration. You can test by going into HSDC Pro, connect to TSW and select ADC. Go to Capture Options and increase the number of captures. The tool will coerce the input to a valid sample count.

    Regards,
    Brian
  • Majid,

    The TSW1406EVM does not support triggering. I would suggest you go with #7 and use the DAC38J8x and TSW14J56. With this setup, there is an option to send a trigger pulse out after a SYSREF pulse. With both boards synchronized to a common reference signal, this would be your best chance to accomplish what you are trying to do. The one concern is that the data going from the TSW14J56 to the DAC will be going though elastic buffers with a fixed amount of delay. The same is true for the ADC data going through the FPGA on the other TSW14J56. This should be a fixed amount of delay but not sure if this will be an issue for you or not. This setup will also require two synchronized reference clocks that would go to the LMK parts used on the ADC and DAC EVM's to synchronize the two.

    Regards,

    Jim 

  • Jim - Thanks for the clarification on the TSW1406.

    I assume the synchronization of the ADC and DAC EVMs is done with a common 10MHz reference going to both boards, correct?

    The fixed delay should not be an issue, I assume it does not vary with power cycling? In that case we can calibrate it out.

    Thanks
  • Majid,

    That is correct regarding the 10MHz. Per the JESD standard, the delay should be fixed with power cycling.

    Regards,

    Jim