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ADC32RF42: poor harmonic performance and questions on correct configuration

Brian Antheunisse
Expert 5195 points
Part Number: ADC32RF42

Hi guys, 

My customer is asking about the ADC32RF42 that they have on a proto board. They are claiming that the harmonic performance is poor, and are asking for some help making sure they have things configured and calibrated correctly. 

They are also concerned with issues about freezing the offset corrector block. 

Is there like a config file or something in the GUI they can export for you guys to look to see how they have things configured? 

Thanks,

Brian 

  • 0
    TI__Expert 4880 points
    Hey Brian,

    I forwarded your question to a device owner. He will get back with you shortly.

    Thanks.

    Yusuf
  • 0 in reply to Yusuf%20Agoro
    TI__Expert 5195 points

    Thanks!

    I have significantly more details from my customer (including a config file) to share as well to help the device owner help us:

    "I recently received the register settings that our contracted board designer uses to initialize the ADC32RF42. My first concern was that the incorrect Nyquist zone was selected, and it looks like the device is configured for 1st Nyquist. I think our first step is to understand how we should initialize the ADC for use in our application.

    We are using the ADC32RF42 to sample a 1GHz (+/- 250MHZ) IF at 1333 1/3 MSPS. The JESD is set for 42810 mode, so we are getting 12-bit samples at a rate of Fs/10. I’m not sure what other information is necessary for configuration. Let me know and I’ll fill in the blanks. I’ve included the register file for reference. It would be great to get something back in the same format.

    It is my hope that the harmonic products that I observed are due to the NL_config for nyq1. I am also concerned about the offset IL spur that is at Fs/4, as that falls in line with the center frequency of my signal. For now, I am ‘freezing’ the offset corrector block."

    Here is the config file:

    IV_MWidebandHwInit.txt 
    #define ADC_MAGIC_SLEEP_REG 0xffff
//ADC Register MAP, taken from ADC32RF45_LMFS_42810.cfg (given to us by TI)
struct {
    uint16_t usAddr;
    uint8_t ucVal;
} grInternalAdcInitCmds[] =
{
//42810

///ADC32RF42/ConfigFiles_ADC32RF42_ NYQUIST1/Powerup_Analog_Config.cfg
//ADC32RFxx_LOWLEVEL
{ 0x0000, 0x81 },      // Global software reset. Remember the sequence of programming the config files is Powerup_Analog_Config-->IL_Config_Nyqx_chA-->IL_Config_Nyqx_chB-->NL_Config_Nyqx_chA-->NL_Config_Nyqx_chB-->JESD_Config
{ 0x0011, 0xFF },      // Select ADC page.
{ 0x0022, 0xC0 },   // Analog trims start here.
{ 0x0032, 0x80 },   // ...
{ 0x0033, 0x08 },   // ...
{ 0x003F, 0x00 },
{ 0x0042, 0x03 },   // ...
{ 0x0043, 0x03 },   // ...
{ 0x0045, 0x58 },   // ...
{ 0x0046, 0xC4 },   // ...
{ 0x0047, 0x01 },   // ...
{ 0x0053, 0x01 },   // ...
{ 0x0054, 0x08 },   // ...
{ 0x0064, 0x05 },   // ...
{ 0x0072, 0x84 },   // ...
{ 0x008C, 0x80 },   // ...
{ 0x0097, 0x80 },   // ...
{ 0x00F0, 0x38 },   // ...
{ 0x00F1, 0xBF },   // Analog trims ended here.
{ 0x0011, 0xCC }, //  Power down of unused cores
{ 0x0020, 0xD0 },
{ 0x0031, 0xE0 },
{ 0x0043, 0x83 }, 
{ 0x0062, 0x80 },
{ 0x0063, 0x01 },
{ 0x004D, 0x01 },
{ 0x0011, 0x00 },   // Disable ADC Page
{ 0x0011, 0x00 },   // Disable ADC Page
{ 0x0012, 0x04 },   // Select Master Page
{ 0x0058, 0x20 },
{ 0x0025, 0x01 },   // Global Analog Trims start here.      
{ 0x0026, 0x40 }, //...
{ 0x0027, 0x80 }, //...
{ 0x0029, 0x40 }, //...
{ 0x002A, 0x80 }, //...
{ 0x002C, 0x40 }, //...
{ 0x002D, 0x80 }, //...
{ 0x002F, 0x40 }, //...
{ 0x0034, 0x01 }, //...
{ 0x003F, 0x01 }, //...
{ 0x0039, 0x50 }, //...
{ 0x003B, 0x2C }, //...
{ 0x0040, 0x80 }, //...   
{ 0x0042, 0x40 }, //...
{ 0x0043, 0x80 }, //...
{ 0x0045, 0x40 }, //...
{ 0x0046, 0x80 }, //...
{ 0x0048, 0x40 }, //...
{ 0x0049, 0x80 }, //...
{ 0x004B, 0x40 }, //...
{ 0x0053, 0x60 }, //...
{ 0x0059, 0x02 }, //...
{ 0x005B, 0x08 }, //...
{ 0x005c, 0x07 }, //...
{ 0x0057, 0x10 },   // Register control for SYSREF --these lines are added in revision SBAA226C.
{ 0x0057, 0x18 },   // Pulse SYSREF, pull high --these lines are added in revision SBAA226C.
{ 0x0057, 0x10 },   // Pulse SYSREF, pull back low --these lines are added in revision SBAA226C.
{ 0x0057, 0x18 },   // Pulse SYSREF, pull high --these lines are added in revision SBAA226C.
{ 0x0057, 0x10 },   // Pulse SYSREF, pull back low --these lines are added in revision SBAA226C.
{ 0x0057, 0x00 },   // Give SYSREF control back to device pin --these lines are added in revision SBAA226C.
{ 0x0012, 0x00 }, // Master page disabled
{ 0x0011, 0xFF }, // Select ADC Page
{ 0x0083, 0x07 },  // Additioanal Analog trims
{ 0x005C, 0x00 },  //...
{ 0x005C, 0x01 },  //...
{ 0x0011, 0x00 },  //Disable ADC Page. Power up Analog writes end here. Program appropriate -->IL_Config_Nyqx_chA-->IL_Config_Nyqx_chB-->NL_Config_Nyqx_chA-->NL_Config_Nyqx_chB-->JESD_Config
{ 0x4001, 0x00 }, //DC corrector Bandwidth settings
{ 0x4002, 0x00 }, //...
{ 0x4003, 0x00 }, //...
{ 0x4004, 0x61 }, //...
{ 0x6068, 0x42 }, //...
{ 0x4003, 0x01 }, //...
{ 0x6068, 0x42 }, //...



///ADC32RF42/ConfigFiles_ADC32RF42_ NYQUIST1/IL_Config_Nyq1_chA.cfg
//ADC32RFxx_LOWLEVEL
{ 0x4001, 0x00}, //Select Main Digial Page. Remember the sequence of programming the config files is Powerup_Analog_Config-->Nyquist_x_config1-->Nyquist_x_Config2-->JESD_Config
{ 0x4002, 0x00}, //...    
{ 0x4003, 0x00}, //...    
{ 0x4004, 0x61}, //...   
{ 0x6000, 0x02}, //...
{ 0x4001, 0x00}, //...    
{ 0x4002, 0x00}, //...    
{ 0x4003, 0x00}, //...    
{ 0x4004, 0x6a}, //...   
{ 0x6012, 0x44}, //...
{ 0x4001, 0x00}, //...
{ 0x4002, 0x00}, //...
{ 0x4004, 0x68}, //...
{ 0x4003, 0x00}, //Main digital page selected for chA
{ 0x6042, 0x3C}, //Program global settings for Interleaving Corrector
{ 0x6043, 0x26}, //...
{ 0x6044, 0x01}, //...
{ 0x6045, 0x10}, //...
{ 0x6049, 0x80},   //...
{ 0x604a, 0x02}, //...
{ 0x604B, 0x03},   //...
{ 0x6053, 0x00},   //...
{ 0x6056, 0x75},   //...
{ 0x6057, 0x75},   //...
{ 0x605A, 0x06}, //...
{ 0x605E, 0x01},   //...
{ 0x6062, 0x00},   //...
{ 0x6068, 0x04},   //...
{ 0x6069, 0x00},   //...
{ 0x6071, 0x20},   //...
{ 0x607D, 0x03},   //...
{ 0x6080, 0x0F},   //...
{ 0x6081, 0xCB},   //...
{ 0x608B, 0x20},   //...
{ 0x608C, 0x08},   //...
{ 0x608D, 0x64},   //...
{ 0x608F, 0x0C},   //...
{ 0x6096, 0x0F},   //...
{ 0x6097, 0x26},   //...
{ 0x6098, 0x00},   //...
{ 0x6099, 0x08},   //...
{ 0x609C, 0x08},   //...
{ 0x609D, 0x20},   //...
{ 0x60A2, 0x08},   //Progam nyquist zone 2 for chA, nyquist zone = 1 : 0x08, nyquist zone = 2 : 0x09, nyquist zone = 3 : 0x0A
{ 0x60A5, 0x7D},   //...
{ 0x60A9, 0x0B},   //...
{ 0x60AA, 0x00}, //...
{ 0x60AB, 0x77},   //...
{ 0x60AC, 0x01},   //...    
{ 0x60AD, 0x77},   //...
{ 0x60AE, 0x01},   //...
{ 0x60BE, 0x03},   //...
{ 0x60FF, 0xC0},   //...
{ 0x6000, 0x00},   // Dig Core reset
{ 0x6000, 0x01},   //...
{ 0x6000, 0x00},   //...







///ADC32RF42/ConfigFiles_ADC32RF42_ NYQUIST1/IL_Config_Nyq1_chb.cfg
//ADC32RFxx_LOWLEVEL
{ 0x4001, 0x00}, //Select Main Digial Page. Remember the sequence of programming the config files is Powerup_Analog_Config-->Nyquist_x_config1-->Nyquist_x_Config2-->JESD_Config
{ 0x4002, 0x00}, //...    
{ 0x4003, 0x01}, //...    
{ 0x4004, 0x61}, //...   
{ 0x6000, 0x02}, //...
{ 0x4004, 0x6a}, //...    
{ 0x6013, 0x01}, //...
{ 0x6014, 0x80}, //...
{ 0x4001, 0x00}, //Select Main Digial Page. Remember the sequence of programming the config files is Powerup_Analog_Config-->Nyquist_x_config1-->Nyquist_x_Config2-->JESD_Config
{ 0x4002, 0x00},
{ 0x4003, 0x01},  //Main digital page selected for chB
{ 0x4004, 0x68},
{ 0x6049, 0x80}, //Special setting for chB
{ 0x6042, 0x20}, //Special setting for chB
{ 0x60A2, 0x08},   //Progam nyquist zone 2 for chB nyquist zone = 1 : 0x08 nyquist zone = 2 : 0x09 nyquist zone = 3 : 0x0A
{ 0x60AA, 0x00}, //...
{ 0x4003, 0x00},  //Main digital page selected for chA
{ 0x6000, 0x00},   // Dig Core reset
{ 0x6000, 0x01},   //...
{ 0x6000, 0x00},   //...
{ 0x0012, 0x04}, //Unused ADC SHA and sp_clk of channel Bpowerdown
{ 0x0011, 0x00}, //...
{ 0x003E, 0xCC}, //...
{ 0x0033, 0xCC}, //...
{ 0x0052, 0x40}, //...
{ 0x0034, 0x01}, //...
{ 0x0036, 0x40}, //...
{ 0x0012, 0x00}, //...


{ ADC_MAGIC_SLEEP_REG, 100 },//Sleep for 50 msec (page 108 of adc32RF42 datasheet



///ADC32RF42/ConfigFiles_ADC32RF42_ NYQUIST1/NL_Config_Nyq1_chA_Band_0_250M.cfg
//ADC32RFxx_LOWLEVEL
{ 0x4001, 0x00}, //chA Non Linearity Trims for Nyq1. Remember the sequence of programming the config files is Powerup_Analog_Config-->IL_Config_Nyqx_chA-->IL_Config_Nyqx_chB-->NL_Config_Nyqx_chA-->NL_Config_Nyqx_chB-->JESD_Config
{ 0x4002, 0xF7}, //...
{ 0x4003, 0x00}, //...
{ 0x4004, 0x20}, //...
{ 0x60E0, 0x2d}, //...
{ 0x60E1, 0x10}, //...
{ 0x60F7, 0x1f}, //...
{ 0x60F8, 0x12}, //...
{ 0x4002, 0xF8}, //...
{ 0x600E, 0x2d}, //...
{ 0x600F, 0x10}, //...
{ 0x6025, 0x1f}, //...
{ 0x6026, 0x12}, //...
{ 0x603C, 0xf9}, //...
{ 0x603D, 0xfe}, //...
{ 0x6053, 0xf8}, //...
{ 0x6054, 0xfe}, //...
{ 0x606A, 0xf9}, //...
{ 0x606B, 0xfe}, //...
{ 0x6081, 0xf8}, //...
{ 0x6082, 0xfe}, //...
{ 0x6098, 0x0 }, //...
{ 0x6099, 0x0 }, //...
{ 0x60AF, 0xff}, //...
{ 0x60B0, 0x0 }, //...
{ 0x60C6, 0x0 }, //...
{ 0x60C7, 0x0 }, //...
{ 0x60DD, 0xff}, //...
{ 0x60DE, 0x0 }, //...
{ 0x60F4, 0xFF}, //...
{ 0x60F5, 0x00}, //...
{ 0x60F6, 0x0 }, //...
{ 0x60F7, 0x0 }, //...
{ 0x60F8, 0x0 }, //...
{ 0x60FB, 0x01}, //...
{ 0x60FC, 0x01}, //...
{ 0x60FD, 0x18}, //...
{ 0x60FF, 0x2 }, //...
{ 0x4002, 0xF9}, //...
{ 0x6004, 0x40}, //...
{ 0x6005, 0x80}, //...
{ 0x6006, 0x00}, //...
{ 0x6008, 0x40}, //...
{ 0x6009, 0x80}, //...
{ 0x600A, 0x00}, //...
{ 0x600C, 0xFF}, //...
{ 0x600D, 0x01}, //...
{ 0x6010, 0xAA}, //...
{ 0x6012, 0x00}, //...
{ 0x4001, 0x00}, //...
{ 0x4002, 0x01}, //...
{ 0x4003, 0x01}, //...
{ 0x4004, 0x20}, //...
{ 0x6048, 0x00}, //...
{ 0x4004, 0x61}, //...
{ 0x4003, 0xF0}, //...
{ 0x4002, 0x01}, //...
{ 0x4001, 0x00}, //...
{ 0x6078, 0x0 }, //...
{ 0x607C, 0x0 }, //...
{ 0x6080, 0x0 }, //...
{ 0x608C, 0x40}, //...
{ 0x608D, 0x80}, //...
{ 0x608E, 0x00}, //...
{ 0x6090, 0xFF}, //...
{ 0x6091, 0x01}, //...
{ 0x6074, 0x1 }, //...
{ 0x6088, 0x00}, //...
{ 0x6070, 0x01}, //...
{ 0x6084, 0x00}, //...




///ADC32RF42/ConfigFiles_ADC32RF42_ NYQUIST1/NL_Config_Nyq1_chB_Band_0_250M.cfg
//ADC32RFxx_LOWLEVEL
{ 0x4003, 0x00}, //chB Non Linearity Trims for Nyq1. Remember the sequence of programming the config files is Powerup_Analog_Config-->IL_Config_Nyqx_chA-->IL_Config_Nyqx_chB-->NL_Config_Nyqx_chA-->NL_Config_Nyqx_chB-->JESD_Config
{ 0x4004, 0x20}, //...
{ 0x4002, 0xF9}, //...
{ 0x6018, 0x26}, //...
{ 0x6019, 0x10}, //...
{ 0x602F, 0x1f}, //...
{ 0x6030, 0x11}, //...
{ 0x6046, 0x26}, //...
{ 0x6047, 0x10}, //...
{ 0x605D, 0x1f}, //...
{ 0x605E, 0x11}, //...
{ 0x6074, 0xfa}, //...
{ 0x6075, 0xfe}, //...
{ 0x608B, 0xf9}, //...
{ 0x608C, 0xfe}, //...
{ 0x60A2, 0xfa}, //...
{ 0x60A3, 0xfe}, //...
{ 0x60B9, 0xf9}, //...
{ 0x60BA, 0xfe}, //...
{ 0x60D0, 0xfe}, //...
{ 0x60D1, 0x0 }, //...
{ 0x60E7, 0x0 }, //...
{ 0x60E8, 0x0 }, //...
{ 0x60FE, 0xfe}, //...
{ 0x60FF, 0x0 }, //...
{ 0x4002, 0xFA}, //...
{ 0x6015, 0x0 }, //...
{ 0x6016, 0x0 }, //...
{ 0x602C, 0xFF}, //...
{ 0x602D, 0x00}, //...
{ 0x602E, 0x0 }, //...
{ 0x602F, 0x0 }, //...
{ 0x6030, 0x0 }, //...
{ 0x6033, 0x01}, //...
{ 0x6034, 0x01}, //...
{ 0x6035, 0x18}, //...
{ 0x6037, 0x2 }, //...
{ 0x603C, 0x40}, //...
{ 0x603D, 0x80}, //...
{ 0x603E, 0x00}, //...
{ 0x6040, 0x40}, //...
{ 0x6041, 0x80}, //...
{ 0x6042, 0x00}, //...
{ 0x6044, 0xFF}, //...
{ 0x6045, 0x01}, //...
{ 0x6048, 0xAA}, //...
{ 0x604A, 0x00}, //...
{ 0x4001, 0x00}, //...
{ 0x4002, 0x01}, //...
{ 0x4003, 0x01}, //...
{ 0x4004, 0x20}, //...
{ 0x6049, 0x00}, //...
{ 0x4004, 0x20}, //...
{ 0x4003, 0x01}, //...
{ 0x4002, 0x06}, //...
{ 0x4001, 0x00}, //...
{ 0x6084, 0x3F}, //...
{ 0x6086, 0x3F}, //...
{ 0x4004, 0x61}, //...
{ 0x4003, 0xF1}, //...
{ 0x4002, 0x01}, //...
{ 0x4001, 0x00}, //...
{ 0x6078, 0x0 }, //...
{ 0x607C, 0x0 }, //...
{ 0x6080, 0x0 }, //...
{ 0x608C, 0x40}, //...
{ 0x608D, 0x80}, //...
{ 0x608E, 0x00}, //...
{ 0x6090, 0xFF}, //...
{ 0x6091, 0x01}, //...
{ 0x4004, 0x61}, //...
{ 0x4003, 0xF1}, //...
{ 0x4002, 0x01}, //...
{ 0x4001, 0x00}, //...
{ 0x6074, 0x1 }, //...
{ 0x6088, 0x00}, //...
{ 0x6070, 0x01}, //...
{ 0x6084, 0x00}, //...
{ 0x4001, 0x00}, //...
{ 0x4002, 0x00}, //...
{ 0x4003, 0x00}, //...
{ 0x4004, 0x68}, //...
{ 0x6068, 0x00}, //...
{ 0x0011, 0x00}, //...
{ 0x0012, 0x04}, //...
{ 0x005c, 0x07}, //...
{ 0x0012, 0x00}, //...


///ADC32RF42/ConfigFiles_ADC32RF42_ NYQUIST1/JESD_Config.cfg
//ADC32RFxx_LOWLEVEL
{ 0x4002, 0x00},   //JESD Interface Programming. Remember the sequence of programming the config files is Powerup_Analog_Config-->IL_Config_Nyqx_chA-->IL_Config_Nyqx_chB-->NL_Config_Nyqx_chA-->NL_Config_Nyqx_chB-->JESD_Config
{ 0x4003, 0x00},
{ 0x4004, 0x69},
{ 0x6002, 0x0F},      // enable LMFS=42810 12-bit mode
{ 0x7002, 0x0F},
{ 0x6037, 0x01},      // PLL DIV mode to 8 0x01
{ 0x7037, 0x01},



//Not in the procedure in the setup files, but it is for the DDC files...
//Disable SYSREF
{ 0x0012, 0x04 }, //master select
{ 0x0020, 0x10 }, //power down sysref 0x10
{ 0x0012, 0x00 }, //master select

};

    Thanks,

    Brian 

  • 0 in reply to Brian Antheunisse
    TI__Guru* 91947 points

    Brian,

    Have the customer try the configuration file I have attached. This was used to capture data per the customers settings. There are a few settings added from the design team. Attached is the data captured as well.

    Regards,

    Jim

    ADC32RF45_LMFS_42810_cust.cfgFs=1.33G_42810.pptx

  • 0 in reply to jim s
    TI__Expert 5195 points

    Jim,

    Customer finally got the chance to try your configuration, here was their response:

    I tried to configuration file that you provided. I’ve inserted my data into the PowerPoint that you sent.

    I was unable to match your results at 1000M. I think the Offset Corrector Block is enabled in the configuration.

    The harmonic levels were equivalent on my hardware. I did notice that some other spurs, especially at 1100MHz, are higher. I’m not sure if these are interleaving spurs, but they show up at 300MHz and 566.666MHz.

    Fs1.33G_42810.pptx

    Regards,

    Brian 

  • 0 in reply to Brian Antheunisse
    TI__Guru* 91947 points

    Brian,

    It appears the customer may have been using 4x interleaving instead of 2x per the config file I sent. This is one reason why they are seeing some of the spurs I did not. The 2x interleaving mode also disables the offset corrector block by default. This may be why they saw the 1000MHz tone attenuate so much as this block will be enabled in 4x mode.

    Regards,

    Jim  

  • 0 in reply to jim s
    TI__Expert 5195 points
    Jim,

    Does the ADC32RF42 even support 4x interleaving? I thought that is a feature of the ‘44 and ’45. I cannot find any reference to it in the datasheet.

    Thanks,
    Brian
  • 0 in reply to Brian Antheunisse
    TI__Guru* 91947 points

    Brian,

    You are correct. The ADC32RF42 only supports 2X interleaving.

    Regards,

    Jim

  • 0 in reply to jim s
    TI__Expert 5195 points

    Jim,

    If this is the case, do you have any other hypotheses on why their part is behaving the way it is? Obviously the 4x interleaving setting is not the issue. 

    Thanks,

    Brian  

  • 0 in reply to Brian Antheunisse
    TI__Guru* 91947 points

    Brian,

    Is there a chance this part is a 44 or 45? Even though it is a 42, if they accidentally program a wrong register, they may get the response they are seeing. I currently do not have a 42 part so I cannot test this right now. Were these last results reported taken with the device using the latest confg file I sent? It appeared to us that the part was configured for 4x interleaving mode.

    Regards,

    Jim 

  • 0 in reply to jim s
    TI__Expert 5195 points
    The ADC32RFxx registers that are in the configuration file that you sent is the only data written to the ADC. [The only thing that is not written are the -6.2dB TX de-emphasis settings (reg 0x0690032-35 and 0x1690032-35).]

    We are stumped.

    Thanks,
    Brian
  • 0 in reply to Brian Antheunisse
    TI__Guru* 91947 points

    Brian,

    We are waiting to here from the design team. I think there are a couple of registers that need to be set to prevent the ADC from notching out the signal at Fs/4 with this part and it is not occurring like it should by default.

    Regards,

    Jim

  • 0 in reply to jim s
    TI__Expert 5195 points
    Ok, thank you. Let me know if you've heard from the design team yet.

    Regards,
    Brian
  • 0 in reply to Brian Antheunisse
    Prodigy 60 points

    Hi,

    Has there been any progress on this issue?

    We are using the ADC32RF42 and have similar questions regarding interleaving correction.

    A few posts ago it was stated that in the 2 interleaved ADC architecture interleaving correction must be bypassed?

    Thanks

    -Brian

  • 0 in reply to Brian Onorato
    Prodigy 60 points

    These are questions that we would greatly appreciate feedback on:

    1. Is this a two or four interleaved ADC architecture?

    2. If the answer to question 1 is two is interleaving correction possible?

    3. Our frequency plan places the signal of interest at Fs/4.  Can interleaving correction still be used in this case?

    Thanks

    -Brian

  • 0 in reply to Brian Onorato
    TI__Expert 5195 points

    Brian,

    Still waiting on design team to comment, and Jim to relay here. 

    By the way, you will probably get better luck posting your own questions as a new post (at the top of this screen there should be a "ask related question" button). 

    Thanks,

    Brian A