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ADS8691: Unexpected time delay between input and output (it is neither conversion time nor acquisition time)

Part Number: ADS8691

I'm using the ADS8691 in a trigger device. The trigger is being generated as soon as the signal (50Hz) crosses a certain level.
I did not expect, that there's a constant time delay of more than 16 samples (sampling rate is 1MSPS) between trigger and real crossing of set level.
I could not find any information regarding time delay in the datasheet of the ADS8691.
The signal processing is done in a FPGA where additional time delay is negligible.

Since there is a low-pass-filter implemented in the ADC I suppose that it is done using FIR, isn't it?

I just wanted to be sure, that there is no other reason for this behavior than the ADC, especially the LPF itself.
Unfortunately, there's no possibility to switch off LPF...

  • Hi Patrick,

    Welcome to E2E forum.

    The LPF inside ADS8691 is an analog second-order, antialiasing LPF. The ADS8691 can convert the analog input signal and output the conversion data during the same cycle(1us for 1Msps sampling rate), also since your input signal is only 50Hz, so the internal LPF should not have an influence and the delay should not be longer.

    Can you please do a test to use ADS8691's input alarm feature? 

    • Eanble ALARM output on the multi-function pin(Alarm/SDO-1/GPO) by programming SDO1_CONFIG[1:0] of the SDO_CTL_REG register to 01b
    • Program ALARM_H_TH_REG and ALARM_L_TH_REG registers with a proper value for a certain input signal level
    • Monitor Alarm pin 14 on ADS8691's TSSOP package and your analog input signal synchronously, check the delay between these two signals.

    Thanks.

    Best regards

    Dale

  • Hi Patrick,
    I will close this thread because it has opened for one week, please follow the suggestion and let me know if you have further question, thanks.
    Best regards
    Dale
  • Hi Dale
    The alarm output is always "high". Even when the ALARM_H_TH_REG and ALARM_L_TH_REG registers are left with their reset values.
    To check, whether the programming is done properly, I configured the output as GPO and set GPO_VAL as 0 and then back to 1. This works fine.
    VDD is okay (5.0V) and shouldn't set an alarm.
  • Hi Patrick,
    Since ADS8691 is 18-bit ADC, but the threshold for Alarm is still 16-bit, so I will check with team and get back to you soon. I have few questions:
    1. What's your command to program SDO_CTL_REG register?
    2. What's your command to program Alarm_TH_REG registers?
    3. Can you please read Alarm_Reg register to check alarm status?
    Thanks.
    Best regards
    Dale
  • Hi Dale
    Thanks for your quick answer.

    1. What's your command to program SDO_CTL_REG register?

    This is the command for register at address 0Ch:
    WHEN "111" => data_out <= "11010010000011000000000100000000";


    2. What's your command to program Alarm_TH_REG registers?

    The command for register 24h (ALARM_H_TH_REG, INP_ALRM_HIGH_TH):
    WHEN "101" => data_out <= "11010000001001001000000000010100";
    -- 131152 = 20050h   = 1000 0000 0001 0100 (00)

    For the hysteresis register 26h (ALARM_H_TH_REG, INP_ALRM_HYST):
    WHEN "110" => data_out <= "11010010001001101000000000000000";
    -- 64 = 40h  = 1000 0000

    Register for Low-Level is left as it is after reset (= 0000h) --> no command.

    Since input range is set to +/-2.56V, alarm should be triggered when input is 1.5mV above 0V (or at -2.56V).


    3. Can you please read Alarm_Reg register to check alarm status?

    For this I have to add some vhdl code first..........

    Best regards
    Patrick

  • Hi Patrick,
    Your commands and calculation are correct, I have few questions:
    1. What's the analog input signal applied to the input of ADC when you did Alarm test?
    2. Was your ADC conversion code correct corresponding to the analog input voltage?
    Thanks.
    Best regards
    Dale
  • The issue is supposed to be solved since I did not get a response during past 2weeks, so this query will be closed, thanks.