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ADS8326: question about timing spec of ADS8326

Part Number: ADS8326

Dear Specialists,

My customer is considering ADS8326 and has questions about timing spec.

I would be grateful if you could advise.

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Could you please see the figure and answer these questions.

(1) Is it possible to expand the Dclock?

(2)How much is the minimum CS high time?

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I appreciate your great help in advance.

Best regards,

Shinichi

  • Hello Shinichi,

    I will need to investigate to see if we can get some exact numbers, but maybe this will help.

    1.  DCLOCK can be as low as 24kHz, so the delay between CS going low and the first clock rising edge in this case is ~1/Fs, or 41.5uS.  The datasheet only specifies a minimum setup time, tsucs of 20nS, and no maximum.

    2.  Assuming a maximum clock rate of 6MHz, and a minimum cycle time of 4uS, CS high in this case is a maximum of 4uS-22*167nS = 333nS.

    The customer may want to consider the ADS8864.  It is a similar device, but has a more flexible digital interface.

    Regards,

    Keith N.

    Precision ADC Applications

  • In reply to Keith Nicholas:

    Hi Keith,

    Thank you for your reply.

    I'll share your suggestion with the customer.

    If he has an additional question, I consult you.

    I appreciate your great help.

    Best regards,
    Shinichi
  • In reply to Shinichi1:

    Hi Keith,

    I sent your answer to the customer and he has additional questions.

    I was wondering if you could advise.

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    I'd like to know details of 333ns.

    I am thinking of ADS8326 inside.

    (1) Is there any clock generator for detecting DCLK in the ADS8326 inside?

    If so, it is operating double (at least 12MHz) and using it to detect CS edge.
    In this case, set up and hold time is 83ns(=1/12MHz) or 166ns(=1/6MHz), is it correct?

    (2) Or the device is using DCLK directly?
    As you mentioned, the value obtained by subtracting 22 DCLK from 4 us (1/250 ksps) becomes 333 ns,
    but the actual CS logic may be able to operate at a much earlier time.
    For example 1 CLK .

    ---

    I appreciate your great help.

    Best regards,
    Shinichi
  • In reply to Shinichi1:

    Hello Shinichi,

    (1) There is not an internal clock in ADS8326; the entire operation from sample to conversion is determined directly by DCLOCK. The internal state machine for the ADS8326 is reset on the falling edge of CS, and then each falling edge of DCLOCK is used for the sample and conversion algorithm and to present the results onto DOUT.
    (2) For the maximum sample frequency of 250kHz and 6MHz DCLOCK, the minimum time that CS must be low is 22*166.67ns = 3.667uS. You can start another conversion after 4uS, which leaves at most 333nS for CS high. As long as your code keeps CS high for 333nS or more, then you will not have any CS high timing issues. The timing for CS high is likely lower, and may be 1 DCLOCK or less, but I am still trying to determine the exact number.

    Regards, Keith
  • In reply to Keith Nicholas:

    Hi Keith,

    Thank you for your reply.

    I understand ADS8326 is directly using DCLOCK.

    Colud you confirm the exact number of minimun CS High time.

    I think it's a very helpful information for the customer, because he'd like to expand the DCLOCK when sample and make the clock faster when convert.

    In this case, cs time affects the total sampling time.

    I appreciate your great help and look forward to waiting your suggestion.

    Best regards,

    Shinichi 

  • In reply to Shinichi1:

    Hi Shinichi,

    CS High time should be at least 1 DCLOCK cycle. At maximum DCLOCK of 6MHz, this would be 166.7nS.

    Regards, Keith N.
  • In reply to Keith Nicholas:

    Hi Keith,

    Thank you for your reply.

    I'll share your information with the customer.

    I appreciate your great help and patience.

    Best regards,
    Shinichi

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