This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Part Number: ADC12DJ3200
I am attempting to use JMODE 16 with Fs=1000MHz. I have confirmed that KM1 and Octets per frame match the other side of the link.
After initialization, I read JESD_STATUS and ALM_STATUS and get these values:
JESD_STATUS (0x208) -> -0x1c (REALIGNED, ALIGNED, PLL_LOCKED)
ALM_STATUS (0x2C1) -> 0x8 (Link Alarm).
There have been times when I have read 0x7c out of JESD_STATUS, but then soon after I read 0x1c.
Sometimes when I clear the REALIGNED bit of JESD_STATUS, it doesn't come back for a while.
The largest spurs in my clock source are about 50 dB down a few kHz away from the main lobe. I have not ever observed Clock Alarm in the ADC.
Any thoughts on what would cause the link to behave this way?
We are glad that we were able to resolve this issue, and will now proceed to close this thread.
If you have further questions related to this thread, you may click "Ask a related question" below. The newly created question will be automatically linked to this question.
In reply to Jim Brinkhurst1:
Hi Jim, thanks for the reply.I am currently using KM1 = 0x1F.Are you referring to SYSREF calibration? I don't have that enabled. Register 0x2B0 -> 0x0 at the moment.My SYSREF frequency is a continuous sine wave at 1.953125 MHz. Is that the correct frequency for sampling 1000 MHz?
In reply to Cameron Grant14:
For KM1 = 1Fh (K Minus 1 = 31d, K = 32d) and Fclk = 1000 MHz the applied SYSREF should be 1.953125 MHz or a sub-harmonic of that frequency.
Please ensure that is the frequency being applied at the ADC SYSREF input. SYSREF must be frequency and phase locked with the ADC CLK signal.
If the frequency is correct and the errors are still happening try disabling SYSREF processing to see if that changes anything.
Set Register 0x029 = 30h (SYSREF_PROC_EN = 0).
If that eliminate the link alarms you are getting then you probably need to use SYSREF Calibration to optimize the setup/hold time between CLK and SYSREF. Please refer to Automatic SYSREF Calibration in the ADC12DJ3200 datasheet to see the steps required.
Does the JESD204B tx state machine in the ADC look like the one in the JEDEC standard? The diagram from the standard (below) makes it look like the only two things that could kick the tx machine out of DATA_ENC are sync_request_tx and reset. I can see now that the sync signal from my receiver is toggling at a frequency that looks similar to the SYSREF frequency. I imagine that is why I am receiving this alarm? Why would my receiver be struggling to get code-group synchronization?
Do you happen to have a JMODE16 example design that uses Xilinx JESD204B cores?
All content and materials on this site are provided "as is". TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with regard to these materials, including but not limited to all implied warranties and conditions of merchantability, fitness for a particular purpose, title and non-infringement of any third party intellectual property right. No license, either express or implied, by estoppel or otherwise, is granted by TI. Use of the information on this site may require a license from a third party, or a license from TI.
TI is a global semiconductor design and manufacturing company. Innovate with 100,000+ analog ICs andembedded processors, along with software, tools and the industry’s largest sales/support staff.