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Part Number: ADS5294
I am aware of the relationship between sample clock jitter and SNR. If I am using a clock generator device, what I am unclear about is which of the jitter specifications I should be using to estimate/calculate the SNR degradation of our system. For example, the clock generator data sheet (si5338) gives random jitter, deterministic jitter, cycle jitter and then an estimated total jitter which is a combination of random and deterministic.
I have seen comparison papers that seem to only use random jitter but not sure why I shouldn't be using the total jitter instead. Do you have any suggestions regarding which of the jitter specs I should use for SNR?
How are you?
Thank you for using TI ADS5294 device.
We will look into your concern about the jitter on the clock
vs. the SNR very soon.
Thank you again!
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In reply to Chen Kung:
Thanks for the information of si5338 device you sent to us.
Its data sheet shows that device can provide the clock jitter of 0.7ps as typical.
However this jitter spec is not low enough for the ADS5294 device's SNR performance
(for example, when ADS5294 is running clock at 80MSPS
and input signal frequency is 65MHz.) to obtain as good as SNR=70.7dB
This result has been shown in the ADS5294 data sheet.
and Please take a look at picture as below:
Here is the reason to explain you how to choose low jitter clock for ADS5294 SNR performance.
Please take a look at the following Figure 5
which also has been modified to be used for ADS5294 device's SNR measurement.
This Figure 5 plot shown is coming from the TI website link:
Please refer to that website as well for more detail information.
This plot shows the Resulting ADC SNR (which is the total jitter already applied to ADS5294 ADC's SNR)
is limited by thermal noise (inside the ADC) and clock jitter (from outside clock generator, for example).
Here we assume our clock jitter (t_jitter) is of 0.4 ps (= 400 fs) performance.
There is one dash line (in black color) showing "fin" (input signal frequency) is running at 65MHz.
then We can see Resulting ADC SNR performance is about 71dB (when fin is at 65MHz).
And then comparing to ADS5294 data sheet, the SNR test result is 70.7dB (very close to 71dB)
(when fin is at 65MHz).
That means in order to let ADS5294 SNR can get the performance as better as 70.7dB,
then we need to provide the input clock source's jitter must be less than or at least equal to 0.4 ps Spec.
So that is the reason why si5338 device's clock jitter is too high for using ADS5294 device.
Thank you very much!
Have a nice day!
Thanks for your detailed explanations. They are very thorough.
I was already aware of the relationship you describe and was really looking for which of the jitter specs provided in the Si5338 were relevant to the SNR calculation you explained above.
Our input bandwidth is only 20MHz (not 65MHz), which would be fine with the ADS5294, even with 0.7ps of jitter. However, the Si5338 also shows cycle-cycle jitter, random jitter and deterministic jitter. Then they provide a total jitter estimate of 13ps pk-pk which is a combination of deterministic and random jitter (see Table 12 of the Si5338 data sheet). 13ps (4.6ps RMS) is much higher than just using the .7ps RMS random jitter spec.
So my question was really whether I should be using the 0.7ps number or the total jitter number. Certainly, 4.6ps would be an issue for us, even with 20MHz BW.
Do you have any thoughts as to which jitter spec. I should be using?
In reply to Robert Servilio19:
Thank you, Chen.
If right now you are using si5338 device to inject one reference input clock
and then generate multiple Low Jitter output clock for ADS5294's CLK IN
or different output clock frequency for other devices' purpose.
Or if you consider to look for other lower jitter clock generator
which is also freq programmable.
TI have one low (cleaning) jitter clock LMK04826 device.
Please take a look at the following data from the datasheet:
Please take a look.
Have a very nice day!
Thanks again, Chen.
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